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1.发明授权公开(公告)号：US08193854B2
公开(公告)日：2012-06-05
申请号：US12651993
申请日：2010-01-04
申请人： Xiao Fei Kuang , Kam Chuen Wan , Kwai Chi Chan , Yat To (William) Wong , Kwok Kuen (David) Kwong
发明人： Xiao Fei Kuang , Kam Chuen Wan , Kwai Chi Chan , Yat To (William) Wong , Kwok Kuen (David) Kwong
IPC分类号： G05F3/02
摘要： A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.
摘要翻译： 带隙参考电路具有用于双向修剪的微调电阻和微调电阻。 PNP晶体管的基极和集电极接地，发射极连接到并联电阻。 差分电阻驱动驱动产生带隙参考电压Vbg的晶体管的运算放大器的反相输入。 感测电阻器将Vbg连接到通过第一并联电阻器连接到非反相输入的分离节点。 分离节点还通过第二并联电阻器连接到反相输入端。 保险丝或开关使能微调和微调电阻。 修整电阻与感测电阻串联，并且减法电阻与将Vbg连接到参考电压Vref的输出电阻串联。 该电路可以设计用于更典型的工艺，因为双向修整允许Vref被升高或降低。 许多电路在针对典型过程时不需要修剪。
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2.发明授权Ultra low voltage multi-stage high-speed CMOS comparator with autozeroing 有权具有自动调零功能的超低压多级高速CMOS比较器公开(公告)号：US08258864B1
公开(公告)日：2012-09-04
申请号：US13238236
申请日：2011-09-21
申请人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F1/02
CPC分类号： H03F3/45183 , H03F3/45636 , H03F2200/261 , H03F2200/294 , H03F2200/453 , H03F2203/45616 , H03F2203/45628
摘要： A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.
摘要翻译： 前级放大器电路可以级联并驱动锁存器，用于精密模数转换器（ADC）。 前置放大器有一个主要部分和一个反馈部分，通过反馈电阻连接，主部分不产生电压降。 偏移量在自动调零阶段存储在偏移电容上，并在放大阶段由传输门隔离。 偏移电容器驱动驱动主部分中的输出节点的反馈晶体管的栅极。 反馈部分中的自动归零陷波晶体管工作在线性区域，而主部分中的电流吸收晶体管工作在饱和区域。 可以添加Kickback电荷隔离晶体管用于电荷隔离。 输出也可以通过均衡的传输门来均衡。 由于折叠的反馈电阻器布置，即使对于具有偏移消除的高速操作也支持非常低的电源电压。
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3.发明授权Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing 有权用于高速低增益比较和高增益自动归零的多级比较器，具有二次差分输入的偏移消除电容公开(公告)号：US07764215B2
公开(公告)日：2010-07-27
申请号：US12347113
申请日：2008-12-31
IPC分类号： H03M1/34
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译： 模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。 最后一个阶段向SAR提供比较信号。 每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。 双输入差分放大器有两对差分输入。 辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。 在放大阶段，初级对通过输入开关连接到级输入。 由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。 在放大期间，双输入差分放大器中的电流吸收器被调高。
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4.发明申请DUAL-USE COMPARATOR/OP AMP FOR USE AS BOTH A SUCCESSIVE-APPROXIMATION ADC AND DAC 有权双使用比较器/运算放大器，用作两个ADC，DAC和DAC公开(公告)号：US20100164761A1
公开(公告)日：2010-07-01
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译： 一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。 一组二进制加权电容器存储模拟输入。 开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。 对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。 分析比较结果以确定模拟输入的最接近的数字值。 在DAC模式下，基于输入数字值切换阵列电容器。 开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。 差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。 可重新配置的比较器级的增益适用于ADC和DAC模式。
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5.发明授权Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC 有权双用比较器/运算放大器用作逐次逼近ADC和DAC公开(公告)号：US07741981B1
公开(公告)日：2010-06-22
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
IPC分类号： H03M1/00
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译： 一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。 一组二进制加权电容器存储模拟输入。 开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。 对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。 分析比较结果以确定模拟输入的最接近的数字值。 在DAC模式下，基于输入数字值切换阵列电容器。 开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。 差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。 可重新配置的比较器级的增益适用于ADC和DAC模式。
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公开(公告)号：US08416107B1
公开(公告)日：2013-04-09
申请号：US13247119
申请日：2011-09-28
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/0682 , H03M1/804
摘要： A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.
摘要翻译： 校准模数转换器（ADC）具有X侧阵列，其具有连接到Y侧线的X侧线和Y侧阵列的二进制加权电容器。 每个阵列具有从最高有效位（MSB）到最低有效位（LSB）的二进制加权电容，但是LSB电容复制为终端电容，并且上下组之间的中间电容也被复制 作为替代电容器。 在校准期间，低阵列电容器切换低电平，而上电容器由X和Y阵列上的温度计代码值驱动。 温度计值反转到X阵列，但在Y阵列上保持不变。 测试较低的阵列位以最终确定平衡X和Y侧电压的校准值。
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7.发明授权Self-starting transistor-only full-wave rectifier for on-chip AC-DC conversion 有权用于片内AC-DC转换的自启动晶体管全波整流器公开(公告)号：US08964436B2
公开(公告)日：2015-02-24
申请号：US13653016
申请日：2012-10-16
IPC分类号： H02M7/5387
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A transistor-based full-wave bridge rectifier is suitable for low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a bridge across the A.C. inputs to produce an internal power voltage. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors with voltages boosted higher than the peak A.C. voltage. Four diode-connected transistors are connected in parallel with the four p-channel bridge transistors to conduct during initial start-up before the comparator and boost drivers operate. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. The transistor bridge can be integrated onto system chips.
摘要翻译： 基于晶体管的全波桥式整流器适用于诸如由射频识别（RFID）设备接收的低交流输入电压。 避免了由桥二极管引起的电压降。 四个p沟道晶体管布置在跨过交流输入的桥中以产生内部电源电压。 比较器接收交流输入并控制升压驱动器的定时，该电压升压驱动器交替地驱动四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。 在比较器和升压驱动器运行之前，四个二极管连接的晶体管与四个p沟道桥式晶体管并联连接，以在初始启动期间导通。 基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。 晶体管桥可以集成到系统芯片上。
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8.发明授权Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge 有权减少残差偏移Σ-Δ模数转换器（ADC），在后沿积分相位结束时具有斩波定时公开(公告)号：US08471744B1
公开(公告)日：2013-06-25
申请号：US13308737
申请日：2011-12-01
IPC分类号： H03M3/00
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译： 模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。 斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。 斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。 以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。 延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。 当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。 该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。
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9.发明申请MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING 有权具有偏移取消电容器的多级比较器，用于高速低增益比较和高增益自动调零的二次差分输入公开(公告)号：US20100164770A1
公开(公告)日：2010-07-01
申请号：US12347113
申请日：2008-12-31
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译： 模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。 最后一个阶段向SAR提供比较信号。 每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。 双输入差分放大器有两对差分输入。 辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。 在放大阶段，初级对通过输入开关连接到级输入。 由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。 在放大期间，双输入差分放大器中的电流吸收器被调高。
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10.发明授权Configurable cascading sigma delta analog-to digital converter (ADC) for adjusting power and performance 有权可配置的级联Σ-Δ模数转换器（ADC），用于调节功率和性能公开(公告)号：US08421660B1
公开(公告)日：2013-04-16
申请号：US13304526
申请日：2011-11-25
IPC分类号： H03M3/00
摘要： A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.
摘要翻译： 级联的Σ-Δ调制器具有多个调制器环路，其具有一组或两组积分器，加法器和定标器，以及产生回路输出的量化器。 对每个环路输入多路复用器，从一个先前的循环中选择一个总体输入或一个环路输出，使调制器回路串联级联或单独运行。 在每个调制器环路之后，滤波器配置的多路复用器选择该环路的输出或来自任何先前循环的回路输出或零。 每个过滤器配置的多路复用器驱动输入到修改后的CIC过滤器。 修改的CIC滤波器具有接收第一滤波器配置多路复用器输出的初始延迟级，以及每个接收连续的滤波器配置多路复用器输出的连续积分器级。 改进的CIC滤波器是数字变换滤波器和级联积分器（CIC） - 滤波器（Cascaded-Integrator-Comb，CIC）滤波器的组合。 调制解调器环路已经掉电，用于低性能配置或级联在一起以实现更高性能的配置。
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