公开(公告)号：US06844757B2

公开(公告)日：2005-01-18

申请号：US10187236

申请日：2002-06-28

Applicant: Conrad Dante

Inventor： Conrad Dante

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17732 ,  G06F7/49936 ,  G06F7/49994

Abstract: A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used within a vector processing block (VPB) that operates on data in vector format. The PLD includes multiple programmable logic blocks that are configurable by a user. The logic blocks operate on data at a bit level resulting in unordered bits of information in a PLD domain. However, a vector processing block operates on data on a vector level (e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc.). Thus, an interface is coupled between the programmable logic blocks and the vector processing block that converts at least a portion of the unordered bits of information from the PLD domain to one or more fixed-width vectors for use in the vector processing block. The interface may also perform scaling and/or sign extension on the unordered bits, to further free up expensive resources in the PLD domain.

Abstract translation: 公开了一种用于将PLD域中的无序位转换为向量域中的固定宽度向量的可编程逻辑器件（PLD）环境的电路。 可以在对矢量格式的数据进行操作的向量处理块（VPB）内使用固定宽度向量。 PLD包括可由用户配置的多个可编程逻辑块。 逻辑块在位电平上对数据进行操作，导致PLD域中的无序位信息。 然而，向量处理块对矢量级数据（例如，8位，16位，32位，64位等）进行操作。 因此，接口耦合在可编程逻辑块和矢量处理块之间，向量处理块将来自PLD域的信息的无序位的至少一部分转换成用于向量处理块中的一个或多个固定宽度向量。 接口还可以在无序位上执行缩放和/或符号扩展，以进一步释放PLD域中的昂贵资源。

公开(公告)号：US6087696A

公开(公告)日：2000-07-11

申请号：US86437

申请日：1998-05-28

Applicant: Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

Inventor： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

IPC: H01L21/28 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L21/28194 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/513 ,  H01L29/517 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/518

Abstract: An improved EEPROM cell structure and a method of fabricating the same is provided so as to improve data retention. The EEPROM cell includes a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barrier so as to suppress leakage current.

Abstract translation: 提供了改进的EEPROM单元结构及其制造方法，以便改善数据保留。 EEPROM单元包括由薄的隧道氧化物层和高k电介质层构成的叠层电介质结构，用作隧道电介质势垒，以便抑制漏电流。

公开(公告)号：US06977408B1

公开(公告)日：2005-12-20

申请号：US10610253

申请日：2003-06-30

Applicant: Chih-Chuan Lin ,  Sunil D. Mehta

Inventor： Chih-Chuan Lin ,  Sunil D. Mehta

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/72

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/7842

Abstract: An EEPROM device exhibiting high saturation current and low signal propagation delay and a process for fabricating the device that includes the formation of refractory metal silicide regions in the source and the drain regions and the gate electrode of an MOS transistor within an EEPROM memory cell. A floating-gate protect layer is formed over the floating-gate electrode and a relatively thick cap oxide layer is formed to overlie the floating-gate protect layer and the source and drain regions and gate electrode of the MOS transistor. A doped oxide layer is formed to overlie the cap oxide layer. The cap oxide layer is formed to a thickness sufficient to create strain in the channel region of the MOS transistor, while not having a thickness that could cause poor data retention in the EEPROM memory cell.

Abstract translation: 具有高饱和电流和低信号传播延迟的EEPROM器件以及制造该器件的方法包括在EEPROM存储单元内的MOS晶体管的源极和漏极区域以及栅极电极中形成难熔金属硅化物区域。 浮栅保护层形成在浮栅电极之上，并且形成相对较厚的盖氧化层以覆盖浮置栅保护层以及MOS晶体管的源极和漏极区域以及栅极电极。 形成掺杂氧化物层以覆盖盖氧化物层。 帽氧化物层形成为足以在MOS晶体管的沟道区域中产生应变的厚度，而不具有在EEPROM存储器单元中可能导致差的数据保持的厚度。

公开(公告)号：US06848095B1

公开(公告)日：2005-01-25

申请号：US10150410

申请日：2002-05-17

Applicant: Chong M. Lee

Inventor： Chong M. Lee

IPC: G06F17/50 ,  G06F19/00

CPC classification number: G06F17/5054

Abstract: A method of assigning logic functions to macrocells assures that a maximum number of macrocells are assigned two or more logic functions. A first logic function is assigned to a macrocell without restriction. Rules are then applied to the macrocell to determine whether a second logic function may be assigned to the macrocell, and, if so, whether any restrictions exist on what the second logic function may be.

Abstract translation: 向宏小区分配逻辑功能的方法确保了最大数量的宏小区被分配两个或多个逻辑功能。 第一逻辑功能被分配给宏小区而不受限制。 然后将规则应用于宏小区以确定是否可以将第二逻辑功能分配给宏小区，并且如果是，则是否存在关于第二逻辑功能可能是什么的任何限制。

公开(公告)号：US5666087A

公开(公告)日：1997-09-09

申请号：US635184

申请日：1996-04-25

Applicant: James L. Gorecki

Inventor： James L. Gorecki

IPC: H03F1/34 ,  G05F3/26 ,  H03F1/08 ,  H03F3/45 ,  H03H11/04

CPC classification number: H03F3/45179 ,  G05F3/262 ,  H03F1/086 ,  H03F3/45197 ,  H03H11/0466 ,  H03F2203/45048 ,  H03F2203/45202 ,  H03F2203/45356 ,  H03F2203/45466 ,  H03F2203/45471

Abstract: An active termination resistor is provided within a feedback loop circuit thus advantageously increasing the stability of the feedback loop circuit. In particular, the active termination resistor traces the impedance of the feedback loop such that R(f).congruent.1/GM3(f). The active resistor may also be configured to track the value of the resistor to set the feedback transconductance over process and temperature variations to ensure stability of the feedback loop over these variations.

Abstract translation: 反馈回路中提供有源终端电阻器，从而有利地增加了反馈回路电路的稳定性。 特别地，有源终端电阻跟踪反馈回路的阻抗，使得R（f）类似1 / GM3（f）。 有源电阻器还可以被配置为跟踪电阻器的值以设置超过过程和温度变化的反馈跨导，以确保反馈回路在这些变化上的稳定性。

公开(公告)号：US5574678A

公开(公告)日：1996-11-12

申请号：US396994

申请日：1995-03-01

Applicant: James L. Gorecki

Inventor： James L. Gorecki

IPC: G06G7/06 ,  G05F3/26 ,  H03F1/08 ,  H03F3/34 ,  H03F3/45 ,  H03H11/04 ,  G06G7/00

CPC classification number: H03F3/45197 ,  G05F3/262 ,  H03F1/086 ,  H03F3/45179 ,  H03F2203/45048 ,  H03F2203/45202 ,  H03F2203/45356 ,  H03F2203/45466 ,  H03F2203/45471

Abstract: A programmable analog circuit apparatus receives a differential analog input signal and provides a processed differential analog output signal. The programmable analog circuit apparatus includes a first input transconductor, a differential amplifiers, and a feedback transconductor. The first input transconductor has a programmable transconductance and includes an input transconductor positive input terminal and an input transconductor negative input terminal and an input transconductor positive output terminal and an input transconductor negative output terminal. The positive and negative input terminals are coupled to receive the differential analog input signal. The differential amplifier includes first and second amplifier input terminals and first and second amplifier output terminals. The positive and negative input transconductor output terminals are coupled to the first and second differential amplifier input terminals. The amplifier output terminals are coupled to the first and second amplifier input terminals. The amplifier provides the processed differential analog output signal via the amplifier output terminals. The feedback transconductor includes a positive feedback transconductor input terminal and a negative feedback transconductor input terminal and a positive feedback transconductor output terminal and a negative feedback transconductor output terminal. The positive and negative feedback transconductor input terminals are coupled to the first and second amplifier output terminals and the positive and negative feedback transconductor output terminals are coupled to the first and second amplifier input terminals. The feedback transconductor output terminals has a high output impedance.

Abstract translation: 可编程模拟电路装置接收差分模拟输入信号并提供经处理的差分模拟输出信号。 可编程模拟电路装置包括第一输入跨导体，差分放大器和反馈跨导体。 第一输入跨导体具有可编程跨导，并且包括输入跨导体正输入端子和输入跨导体负输入端子和输入跨导体正输出端子和输入跨导体负输出端子。 正和负输入端子被耦合以接收差分模拟输入信号。 差分放大器包括第一和第二放大器输入端和第一和第二放大器输出端。 正和负输入跨导体输出端子耦合到第一和第二差分放大器输入端子。 放大器输出端子耦合到第一和第二放大器输入端子。 放大器通过放大器输出端子提供处理后的差分模拟输出信号。 反馈跨导体包括正反馈跨导体输入端子和负反馈跨导体输入端子和正反馈跨导体输出端子和负反馈跨导体输出端子。 正和负反馈跨导体输入端子耦合到第一和第二放大器输出端子，正和负反馈跨导体输出端子耦合到第一和第二放大器输入端子。 反馈跨导体输出端子具有高输出阻抗。

公开(公告)号：US4833646A

公开(公告)日：1989-05-23

申请号：US707670

申请日：1985-03-04

Applicant: John E. Turner

Inventor： John E. Turner

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17704 ,  H03K19/17764 ,  H03K19/1778

Abstract: A programmable logic device is disclosed which is adapted to isolate the Miller capacitances of erased memory cells from the product terms and to limit the cell current drawn through the product term sense amplifiers. The invention substantially reduces the row switching noise coupled onto the product terms, allows high speed sense amplifier operation, and significantly reduces the power dissipated by the device. In accordance with the invention, the electrically erasable sense transistor for each memory cell is disposed between the cell select transistor and the product term sense amplifier, thereby isolating the Miller capacitance associated with the select transistor from the sense amplifier when the cell is in the erased (nonconductive) state. Separate product term ground lines are provided for each product term. A current limiter connects each product term ground line to ground, and is adapted to limit the current flow through each product term to a predetermined maximum level, typically about the maximum current level which may be passed through one conductive memory cell.

Abstract translation: 公开了一种可编程逻辑器件，其适于将擦除的存储器单元的Miller电容与产品项隔离开来，并限制通过乘积项检测放大器获得的单元电流。 本发明大大降低了耦合到产品术语上的行开关噪声，允许高速读出放大器操作，并且显着地降低了器件耗散的功率。 根据本发明，用于每个存储单元的电可擦除感测晶体管设置在单元选择晶体管和产品项检测放大器之间，从而当单元被擦除时将与选择晶体管相关联的米勒电容与读出放大器隔离 （非导通）状态。 为每个产品术语提供单独的产品术语地线。 电流限制器将每个产品术语地线连接到地，并且适于将通过每个乘积项的电流限制到预定的最大电平，通常约为可以通过一个导电存储器单元的最大电流电平。

公开(公告)号：US06981381B1

公开(公告)日：2006-01-03

申请号：US10737514

申请日：2003-12-16

Applicant: Ching Wang ,  Robert M. Bartel ,  Hans W. Klein

Inventor： Ching Wang ,  Robert M. Bartel ,  Hans W. Klein

IPC: F25B21/02

CPC classification number: F25B21/04 ,  F25B2321/0212 ,  G05D23/1919

Abstract: Device driver circuits based on H-bridges can be implemented to provide linear control of the H-bridge, reduce power losses, and reduce certain component size/cost. The driver circuits can use two feedback loops to operate the H-bridge in different regions and to guarantee that current flows through an H-bridge load device, such as a thermoelectric cooler, in only one direction at a given time. The H-bridge driver circuits can remove the possibility of high currents bypassing the load device and thus going directly through the switches on either side of the H-bridge driver. The H-bridge driver circuits also ensure careful control of the current applied to the H-bridge load device. Such driver circuits are particularly useful for controlling the current applied to thermoelectric devices.

Abstract translation: 可以实现基于H桥的器件驱动器电路，以提供H桥的线性控制，降低功耗，并降低某些组件尺寸/成本。 驱动器电路可以使用两个反馈回路来操作不同区域中的H桥，并且确保电流在给定时间仅沿一个方向流过H桥负载装置，例如热电冷却器。 H桥驱动电路可以消除旁路负载装置的高电流的可能性，从而直接通过H桥驱动器两侧的开关。 H桥驱动电路还可以确保对H桥负载装置的电流进行仔细的控制。 这种驱动电路对于控制施加到热电器件的电流特别有用。

公开(公告)号：US06861868B1

公开(公告)日：2005-03-01

申请号：US10463781

申请日：2003-06-16

Applicant: Om P. Agrawal ,  Jinghui Zhu ,  Kuang Chi ,  ChienKuang Chen

Inventor： Om P. Agrawal ,  Jinghui Zhu ,  Kuang Chi ,  ChienKuang Chen

IPC: H01L21/82 ,  H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17744

Abstract: A programmable semiconductor device comprising a plurality of I/O circuits arranged into blocks includes a routing structure for each block, wherein each routing structure may programmably route signals between its block's I/O circuits and the I/O circuits within the remaining blocks. Each I/O circuit associates with a pin such that each block has a set of pins. A SERDES and a FIFO buffer associate with each block. Each block's SERDES couples between the block's I/O circuits and the block's set of pins. Each FIFO buffer couples between the SERDES and its block's I/O circuits.

Abstract translation: 包括布置成块的多个I / O电路的可编程半导体器件包括用于每个块的路由结构，其中每个路由结构可以在其块的I / O电路与剩余块内的I / O电路之间编程地路由信号。 每个I / O电路与引脚相关联，使得每个块具有一组引脚。 SERDES和FIFO缓冲区与每个块相关联。 每个块的SERDES耦合在块的I / O电路和块的引脚组之间。 每个FIFO缓冲器耦合在SERDES和其块的I / O电路之间。

公开(公告)号：US6133750A

公开(公告)日：2000-10-17

申请号：US069035

申请日：1998-04-27

Applicant: Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Allan T. Davidson

Inventor： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Allan T. Davidson

IPC: G06F1/10 ,  H03K19/177

CPC classification number: H03K19/1774 ,  G06F1/10

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.

Abstract translation: 可编程逻辑器件包括全局时钟结构和多个局部时钟结构。 每个局部时钟结构将相应的局部时钟信号分配给可编程逻辑器件的对应部分。 全局时钟结构将全局时钟信号分配给可编程逻辑器件的所有部分。