公开(公告)号：US08542073B2

公开(公告)日：2013-09-24

申请号：US13067328

申请日：2011-05-25

申请人： Tomokazu Matsuzaki ,  Kazutoshi Sako

发明人： Tomokazu Matsuzaki ,  Kazutoshi Sako

IPC分类号： H03K3/26

CPC分类号： H03K3/354 ,  H03K3/017 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/089

摘要： A variable-capacitance device includes a first capacitance element coupled between a first power supply terminal and an output terminal, a capacitance selection switch that is turned on and off in accordance with a capacitance switching signal, a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch, and an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch.

摘要翻译： 可变电容器件包括耦合在第一电源端子和输出端子之间的第一电容元件，根据电容切换信号导通和截止的电容选择开关，与第一电源端子和输出端子并联连接的第二电容元件 电容元件并串联连接到电容选择开关，以及误差校正电路，被配置为在电容选择开关处于截止状态的状态下进行操作，响应于在输出端产生电压的电荷复位信号 端子复位到复位电压，误差校正电路基本上消除了输出端子处的电压与电容切换节点处的电压之间的差异，在该电容开关节点处第二电容元件耦合到电容选择开关。

公开(公告)号：US08009500B2

公开(公告)日：2011-08-30

申请号：US12367871

申请日：2009-02-09

申请人： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

发明人： Koji Nii ,  Shigeki Obayashi ,  Hiroshi Makino ,  Koichiro Ishibashi ,  Hirofumi Shinohara

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/063 ,  G11C11/412

摘要： Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

摘要翻译： 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20110193185A1

公开(公告)日：2011-08-11

申请号：US13088725

申请日：2011-04-18

申请人： Takashi Takenaga ,  Takeharu Kuroiwa ,  Hiroshi Takada ,  Shuichi Ueno ,  Kiyoshi Kawabata

发明人： Takashi Takenaga ,  Takeharu Kuroiwa ,  Hiroshi Takada ,  Shuichi Ueno ,  Kiyoshi Kawabata

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

摘要： There is provided a magnetic memory device stable in write characteristics. The magnetic memory device has a recording layer. The planar shape of the recording layer has the maximum length in the direction of the easy-axis over a primary straight line along the easy-axis, and is situated over a length smaller than the half of the maximum length in the direction perpendicular to the easy-axis, and on the one side and on the other side of the primary straight line respectively, the planar shape has a first part situated over a length in the direction perpendicular to the easy-axis, and a second part situated over a length smaller than the length in the direction perpendicular to the easy-axis. The outer edge of the first part includes only a smooth curve convex outwardly of the outer edge.

摘要翻译： 提供了一种写入特性稳定的磁存储器件。 磁存储器件具有记录层。 记录层的平面形状沿着容易轴在易于轴的方向上在主直线上具有最大长度，并且位于比垂直于该方向的方向上的最大长度的一半长度 分别在主直线的一侧和另一侧上，平面形状具有位于垂直于易轴的方向上的长度的第一部分，以及位于长度方向上的第二部分 小于垂直于易轴方向的长度。 第一部分的外边缘仅包括从外边缘向外凸出的平滑曲线。

公开(公告)号：US07847331B2

公开(公告)日：2010-12-07

申请号：US11030900

申请日：2005-01-10

申请人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

发明人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC分类号： H01L29/792

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

摘要翻译： 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。