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公开(公告)号：US12088429B2
公开(公告)日：2024-09-10
申请号：US17677113
申请日：2022-02-22
发明人： Fred Rennig , Vaclav Dvorak
IPC分类号： H04L12/403 , H03K7/08 , H04L12/40
CPC分类号： H04L12/403 , H03K7/08 , H04L12/40006 , H04L2012/40215
摘要： A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.
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公开(公告)号：US11977438B2
公开(公告)日：2024-05-07
申请号：US17406910
申请日：2021-08-19
发明人： Roberto Colombo
CPC分类号： G06F11/0784 , G06F11/0721 , G06F11/0739 , G06F11/0751 , G06F11/0772 , G06F11/1048
摘要： A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.
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公开(公告)号：US11977424B2
公开(公告)日：2024-05-07
申请号：US17702529
申请日：2022-03-23
IPC分类号： G06F1/24
CPC分类号： G06F1/24
摘要： A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down. During the software runtime phase, the first circuitry activate a weak pull-down for implementing a bidirectional reset terminal or activates a weak pull-up resistance for implementing a reset output terminal, and the second circuitry activates a weak pull-up for implementing a reset input terminal or activates a strong pull-up for implementing a reset output terminal.
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公开(公告)号：US11889594B2
公开(公告)日：2024-01-30
申请号：US17654532
申请日：2022-03-11
申请人： STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics Application GMBH
发明人： Manuel Gaertner , Philippe Sirito-Olivier , Giovanni Luca Torrisi , Thomas Urbitsch , Christophe Roussel , Fritz Burkhardt
IPC分类号： H05B45/14 , H05B45/46 , H05B45/50 , H05B45/325
CPC分类号： H05B45/46 , H05B45/14 , H05B45/325 , H05B45/50
摘要： A system includes lighting devices coupled to output supply pins, a microcontroller circuit, and a driver circuit, which receives data therefrom, and switches coupled in series to the lighting devices. The driver circuit includes output supply pins and selectively propagates a supply voltage to the output supply pins to provide respective pulse-width modulated supply signals at the output supply pins. The driver circuit computes duty-cycle values of the pulse-width modulated supply signals as a function of the data received from the microcontroller circuit. The lighting devices include at least one subset coupled to the same output supply pin. The microcontroller individually controls the switches via respective control signals to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices.
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公开(公告)号：US11853252B2
公开(公告)日：2023-12-26
申请号：US17819749
申请日：2022-08-15
发明人： Fred Rennig , Vaclav Dvorak
CPC分类号： G06F13/4282 , G06F9/30134 , G06F13/28 , G06F13/4072
摘要： A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.
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公开(公告)号：US20230300001A1
公开(公告)日：2023-09-21
申请号：US18174387
申请日：2023-02-24
申请人： STMicroelectronics Application GMBH , STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. , STMicroelectronics S.r.l.
发明人： Fred Rennig , Jochen Barthel , Ludek Beran , Mirko Dondini , Vaclav Dvorak , Vincenzo Polisi , Marianna Sanza' , CalogeroAndrea Trecarichi , Alfonso Furio
IPC分类号： H04L12/40 , H03K19/00 , H03K17/687
CPC分类号： H04L12/40169 , H03K19/0002 , H03K17/6872 , H03K17/6874 , H04L12/40032 , H04L2012/40273 , H04L2012/40215
摘要： In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.
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公开(公告)号：US20230133912A1
公开(公告)日：2023-05-04
申请号：US17515212
申请日：2021-10-29
申请人： STMICROELECTRONICS APPLICATION GMBH , STMicroelectronics S.r.l. , STMicroelectronics International N.V.
IPC分类号： G01R31/317 , G01R31/319 , G01R31/28
摘要： A trace-data preparation circuit including a filtering circuit to receive traced memory-write data and a First In First Out buffer coupled with the filtering circuit to receive selected memory-write data filtered by the filtering circuit. The trace-data preparation circuit further including a data compression circuit to provide packaging data to a packaging circuit that groups the selected memory-write data.
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公开(公告)号：US20230065623A1
公开(公告)日：2023-03-02
申请号：US17815807
申请日：2022-07-28
摘要： A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.
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公开(公告)号：US20230053798A1
公开(公告)日：2023-02-23
申请号：US17819749
申请日：2022-08-15
发明人： Fred Rennig , Vaclav Dvorak
摘要： A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.
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公开(公告)号：US11526458B2
公开(公告)日：2022-12-13
申请号：US17245894
申请日：2021-04-30
发明人： Fred Rennig , Vaclav Dvorak , Ludek Beran
摘要： An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.
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