公开(公告)号：US09373695B2

公开(公告)日：2016-06-21

申请号：US13942400

申请日：2013-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuan-Yu Chen ,  Hsien-Hsin Lin ,  Chun-Feng Nieh ,  Hsueh-Chang Sung ,  Chien-Chang Su ,  Tsz-Mei Kwok

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

CPC分类号： H01L29/66477 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.

公开(公告)号：US20230369397A1

公开(公告)日：2023-11-16

申请号：US18226192

申请日：2023-07-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPAY, LTD.

发明人： Matthias PASSLACK ,  Marcus Johannes Henricus VAN DAL ,  Timothy VASEN ,  Georgios VELLIANITIS

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/0673 ,  H01L29/785 ,  H01L21/02181 ,  H01L21/0217 ,  H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L29/66545 ,  H01L29/0847

摘要： In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

公开(公告)号：US20130270702A1

公开(公告)日：2013-10-17

申请号：US13586676

申请日：2012-08-15

申请人： Chen-Hua YU ,  Shau-Lin SHUE ,  Hsiang-Huan LEE ,  Ching-Fu YEH

发明人： Chen-Hua YU ,  Shau-Lin SHUE ,  Hsiang-Huan LEE ,  Ching-Fu YEH

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76871 ,  H01L21/76846 ,  H01L2221/1089

摘要： A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.

摘要翻译： 一种半导体器件中的铜互连结构，包括形成在半导体器件的电介质层中的开口，该开口具有侧壁和底部。 第一阻挡层保形地沉积在开口的侧壁和底部上。 第一种子层共形沉积在第一阻挡层上。 第二阻挡层被共形沉积在第一籽晶层上。 第二种子层被共形沉积在第二阻挡层上，并且导电塞被沉积在电介质层的开口中。

公开(公告)号：US20120051872A1

公开(公告)日：2012-03-01

申请号：US12869171

申请日：2010-08-26

申请人： Shao-Yen Ku ,  Chi-Ming Yang ,  Chiang Ming-Tsao ,  Yu-Fen Tzeng ,  Chin-Hsiang Lin

发明人： Shao-Yen Ku ,  Chi-Ming Yang ,  Chiang Ming-Tsao ,  Yu-Fen Tzeng ,  Chin-Hsiang Lin

IPC分类号： H01L21/677

CPC分类号： H01L21/67011 ,  H01L21/67155 ,  H01L21/67201 ,  H01L21/677 ,  H01L21/67703 ,  H01L21/67745 ,  H01L21/67772 ,  H01L21/67778 ,  Y10S414/135 ,  Y10S414/139

摘要： The present disclosure provides a system and method for processing a semiconductor substrate wherein a substrate is received at a load lock interface. The substrate is transferred from the load lock interface to a process module using a first module configured for unprocessed substrates. A manufacturing process is performed on the substrate within the process module. Thereafter, the substrate is transferred from the process module to the load lock interface using a second module configured for processed substrates.

摘要翻译： 本公开提供了一种用于处理半导体衬底的系统和方法，其中在负载锁定接口处接收衬底。 使用配置为未处理基板的第一模块将基板从加载锁定接口传送到处理模块。 在处理模块内的基板上进行制造工艺。 此后，使用配置成处理的基板的第二模块将基板从处理模块传送到加载锁定接口。