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    Copper etch scheme for copper interconnect structure
    1.
    发明授权
    Copper etch scheme for copper interconnect structure 有权
    铜互连结构的铜蚀刻方案

    公开(公告)号：US08735278B2

    公开(公告)日：2014-05-27

    申请号：US13550951

    申请日：2012-07-17

    Applicant: Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

    Inventor： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

    IPC: H01L21/4763

    CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

    Abstract translation: 本公开涉及一种制造互连结构的方法，其中在半导体衬底上形成低k电介质层，然后在低k电介质层上形成铜或铜合金层。 铜或铜合金层被图案化和蚀刻以形成具有凹部的铜体，然后填充有低k电介质材料。 该方法允许形成镶嵌结构，而不会遇到由非平面特征和孔隙低K电介质损伤所呈现的各种问题。

    METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
    2.
    发明申请
    METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION 有权
    半导体集成电路制造方法

    公开(公告)号：US20140065818A1

    公开(公告)日：2014-03-06

    申请号：US13599764

    申请日：2012-08-30

    Applicant: Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    Inventor： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    IPC: H01L21/768

    CPC classification number: H01L21/76852 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature.

    Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 牺牲层（SL）在衬底上形成并图案化。 图案化SL具有多个开口。 该方法还包括在开口中形成金属层，然后移除图案化的SL以横向暴露金属层的至少一部分以形成具有与开口基本相同的轮廓的金属特征。 电介质层沉积在金属特征的侧面上。

    Apparatus and method for low contact resistance carbon nanotube interconnect
    3.
    发明授权
    Apparatus and method for low contact resistance carbon nanotube interconnect 有权
    低接触电阻碳纳米管互连的装置和方法

    公开(公告)号：US08624396B2

    公开(公告)日：2014-01-07

    申请号：US13523644

    申请日：2012-06-14

    Applicant: Hsien-Chang Wu ,  Hsiang-Huan Lee ,  Shau-Lin Shue

    Inventor： Hsien-Chang Wu ,  Hsiang-Huan Lee ,  Shau-Lin Shue

    IPC: H01L23/48

    CPC classification number: H01L23/53209 ,  B82Y40/00 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus comprises a first dielectric layer formed over a substrate, a first metal line embedded in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, a second metal line embedded in the second dielectric layer, an interconnect structure formed between the first metal line and the second metal line, a first carbon layer formed between the first metal line and the interconnect structure and a second carbon layer formed between the second metal line and the interconnect structure.

    Abstract translation: 一种装置包括形成在衬底上的第一介电层，嵌入在第一介电层中的第一金属线，形成在第一电介质层上的第二电介质层，嵌入第二电介质层中的第二金属线， 第一金属线和第二金属线，形成在第一金属线和互连结构之间的第一碳层和形成在第二金属线和互连结构之间的第二碳层。

    Copper interconnect structure and method for forming the same
    6.
    发明授权
    Copper interconnect structure and method for forming the same 有权
    铜互连结构及其形成方法

    公开(公告)号：US08941239B2

    公开(公告)日：2015-01-27

    申请号：US13586676

    申请日：2012-08-15

    Applicant: Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

    Inventor： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

    IPC: H01L23/48 ,  H01L21/14

    CPC classification number: H01L21/76871 ,  H01L21/76846 ,  H01L2221/1089

    Abstract: A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.

    Abstract translation: 一种半导体器件中的铜互连结构，包括形成在半导体器件的电介质层中的开口，该开口具有侧壁和底部。 第一阻挡层保形地沉积在开口的侧壁和底部上。 第一种子层共形沉积在第一阻挡层上。 第二阻挡层被共形沉积在第一籽晶层上。 第二种子层被共形沉积在第二阻挡层上，并且导电塞被沉积在电介质层的开口中。

    Low resistance high reliability contact via and metal line structure for semiconductor device
    9.
    发明授权
    Low resistance high reliability contact via and metal line structure for semiconductor device 有权
    低电阻高可靠性接触通孔和半导体器件的金属线结构

    公开(公告)号：US08106512B2

    公开(公告)日：2012-01-31

    申请号：US12845852

    申请日：2010-07-29

    Applicant: Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    Inventor： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

    Abstract translation: 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

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