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公开(公告)号：US20180081695A1
公开(公告)日：2018-03-22
申请号：US15268639
申请日：2016-09-19
CPC分类号： G06F15/7853 , G06F1/24 , G06F9/4401 , G06F12/0246 , G06F13/00
摘要： A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. The memory controller uses the divided clock signal to establish an interface communication frequency with the memory. A boot control logic circuit, connected to the clock divider, compares a check data pattern to a predefined data pattern read from the memory by the memory controller at the interface frequency. When the predefined and check data patterns do not match, the boot control logic circuit instructs the clock divider to adjust the divided clock signal to change the interface frequency, after which the predefined data pattern reading and comparison are repeated, and when the predefined and check data patterns match, the memory controller reads a boot program, executed by the core, from the memory at the interface frequency.
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2.发明授权Scheduling events in a microprocessor using a plurality of delta time registers arranged as a sequence buffer and indicating a sequence position of the sequence buffer to process an event 有权使用多个Δ时间寄存器在微处理器中调度事件，该多个Δ时间寄存器被布置为序列缓冲器并且指示序列缓冲器的序列位置来处理事件公开(公告)号：US08984323B2
公开(公告)日：2015-03-17
申请号：US13247489
申请日：2011-09-28
申请人： Stephen Bowling , Igor Wojewoda
发明人： Stephen Bowling , Igor Wojewoda
CPC分类号： G06F1/14 , G06F1/3243 , G06F1/3287 , G06F15/7814 , G06F15/7853 , Y02D10/152 , Y02D10/171
摘要： A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: —a timer being clocked by an independent clock signal; —a comparator coupled with a timer register of said timer and having an output generating an output signal; —an event register coupled with said comparator; —a delta time register; and —an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.
摘要翻译： 微控制器具有中央处理单元（CPU），多个外围设备和可编程调度器单元，其具有： - 定时器由独立时钟信号计时; - 比较器，与所述定时器的定时器寄存器耦合并具有产生输出信号的输出; - 与所述比较器耦合的事件寄存器; - 时差寄存器 以及 - 由比较器的输出信号和第一和第二输入和输出控制的算术逻辑单元，其中第一输入与定时器寄存器或事件寄存器耦合，第二输入与增量时间寄存器耦合， 输出与事件寄存器耦合。
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公开(公告)号：US20190253417A1
公开(公告)日：2019-08-15
申请号：US16075951
申请日：2017-02-13
发明人： Dong Kyue KIM , Ji-Hoon KIM
CPC分类号： H04L63/0869 , G06F15/7807 , G06F15/7842 , G06F15/7853 , G06F21/55 , G06F21/556 , G06F21/57 , G06F21/60 , G06F21/602 , G06F21/74 , G06F21/85 , G06F2221/2149 , G06K19/07372 , G06Q20/341 , H04L9/321 , H04L9/3263 , H04L9/3278 , H04L2209/12
摘要： A secure semiconductor chip is presented. The semiconductor chip is, for example, a system-on-chip. Processor cores included in the system-on-chip are connected to normal IPs through a system bus. A secure bus, which is a hidden bus physically separated from the system bus, is provided separately. The secure bus is connected to security IPs which perform security functions or handle security data. The secure semiconductor chip may perform necessary authentication by switching a normal mode to a secure mode.
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公开(公告)号：US20130080819A1
公开(公告)日：2013-03-28
申请号：US13247489
申请日：2011-09-28
申请人： Stephen Bowling , Igor Wojewoda
发明人： Stephen Bowling , Igor Wojewoda
IPC分类号： G06F1/14
CPC分类号： G06F1/14 , G06F1/3243 , G06F1/3287 , G06F15/7814 , G06F15/7853 , Y02D10/152 , Y02D10/171
摘要： A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: a timer being clocked by an independent clock signal; a comparator coupled with a timer register of said timer and having an output generating an output signal; an event register coupled with said comparator; a delta time register; and an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.
摘要翻译： 微控制器具有中央处理单元（CPU），多个外围设备和可编程调度器单元，其具有：由独立时钟信号计时的定时器; 比较器，与所述定时器的定时器寄存器耦合并具有产生输出信号的输出; 与所述比较器耦合的事件寄存器; 增量时间寄存器 以及由比较器的输出信号和第一和第二输入和输出控制的算术逻辑单元，其中第一输入与定时器寄存器或事件寄存器耦合，第二输入与增量时间寄存器和 输出与事件寄存器耦合。
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5.发明申请MULTI-CHIP PACKAGED FUNCTION INCLUDING A PROGRAMMABLE DEVICE AND A FIXED FUNCTION DIE AND USE FOR APPLICATION ACCELERATION 审中-公开多芯片封装功能，包括可编程器件和固定功能模块，并用于应用程序加速公开(公告)号：US20160124899A1
公开(公告)日：2016-05-05
申请号：US14719430
申请日：2015-05-22
申请人： eASIC Corporation
发明人： Ronnie VASISHTA , Ban P. WONG
CPC分类号： G06F15/7817 , G06F15/7807 , G06F15/7853 , G06F15/7889 , Y02D10/12 , Y02D10/13
摘要： One or more processing functions may be off-loaded from a general-purpose processing device to auxiliary processing devices. The auxiliary processing devices may include a programmable element and a fixed-function element that may be pre-configured to perform the one or more processing functions. The programmable element and the fixed-function element may be dies of a multi-chip module (MOM) in a common package that can contain the general-purpose processing device, or the general-purpose processing device may reside outside of the MOM.
摘要翻译： 一个或多个处理功能可以从通用处理设备卸载到辅助处理设备。 辅助处理装置可以包括可预先配置为执行一个或多个处理功能的可编程元件和固定功能元件。 可编程元件和固定功能元件可以是可以容纳通用处理装置的通用封装中的多芯片模块（MOM）的裸片，或者通用处理装置可以驻留在MOM之外。
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公开(公告)号：US08843777B2
公开(公告)日：2014-09-23
申请号：US12033990
申请日：2008-02-20
申请人： Wilhard von Wendorff
发明人： Wilhard von Wendorff
CPC分类号： G06F15/7853 , G06F15/7814
摘要： Multiple modules are connected to a signal output module via first and second busses. Different commands may be transmitted on the two busses. Both busses may be hierarchically constructed so that all units are connected one after the other in a chain like manner on the busses. The modules cooperate to transition an output signal between different duty cycles and activate and deactivate responsive to timer comparisons.
摘要翻译： 多个模块通过第一和第二总线连接到信号输出模块。 两个总线上可能会发送不同的命令。 两个总线可以被分层构造，使得所有单元在公共汽车上以链式方式彼此连接。 模块协作以在不同占空比之间转换输出信号，并响应于定时器比较而激活和停用。
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公开(公告)号：US20190236048A1
公开(公告)日：2019-08-01
申请号：US16159729
申请日：2018-10-15
申请人： OMRON Corporation
发明人： Hitoshi OBA , Minoru TAKAHASHI
IPC分类号： G06F15/78 , G01R31/302 , G06F9/54
CPC分类号： G06F15/7867 , G01D18/00 , G01R31/302 , G06F9/54 , G06F15/7853
摘要： According to the disclosure, it is possible to perform comparison with high accuracy even if a deviation in the time axis direction occurs between the target signal and the comparison condition. A control apparatus includes an acquisition part acquiring a time series signal output from a device; a comparison condition storage part storing information indicating a temporal change of a predetermined comparison condition; an area determination part determining a target area, which is an area satisfying a predetermined condition indicating that change of a value is stable, in the signal acquired by the acquisition part; and a comparison part performing comparison with the comparison condition by using a signal of the target area determined by the area determination part.
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公开(公告)号：US20190050702A1
公开(公告)日：2019-02-14
申请号：US16076473
申请日：2017-02-10
发明人： Hyoung Ho KO , Chang-Sik YOO , Byong Deok CHOI
IPC分类号： G06K19/073 , G06Q20/34
CPC分类号： H04L63/0869 , G06F15/7807 , G06F15/7842 , G06F15/7853 , G06F21/55 , G06F21/556 , G06F21/57 , G06F21/60 , G06F21/602 , G06F21/74 , G06F21/85 , G06F2221/2149 , G06K19/07372 , G06Q20/341 , H04L9/321 , H04L9/3263 , H04L9/3278 , H04L2209/12
摘要： Disclosed is a secure semiconductor chip. When a physical attack such as a depackaging attack occurs, the semiconductor chip can detect the physical attack. A semiconductor chip according to one embodiment comprises an energy harvesting element inside a package. The energy harvesting element may comprise, for example, an on-chip photodiode. A depackaging attack causes the generation of a voltage of a photodiode, and thus a change in physical state of the packaging can be detected.
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公开(公告)号：US11940944B2
公开(公告)日：2024-03-26
申请号：US17877531
申请日：2022-07-29
申请人： Intel Corporation
CPC分类号： G06F15/7853 , G11C17/16 , G11C29/789 , G06F2212/202
摘要： A computer platform is disclosed. The computer platform comprises a non-volatile memory to store fuse override data; and a system on chip (SOC), coupled to the non-volatile memory, including a fuse memory to store fuse data and security micro-controller to receive the fuse override data and perform a fuse override to overwrite the fuse data stored in the fuse memory with the fuse override data.
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公开(公告)号：US10037213B2
公开(公告)日：2018-07-31
申请号：US15268639
申请日：2016-09-19
IPC分类号： G06F9/4401 , G06F1/08 , G06F15/78 , G06F12/02
CPC分类号： G06F15/7853 , G06F1/24 , G06F9/4401 , G06F12/0246 , G06F13/00
摘要： A system-on-chip includes a processing core and a memory controller connected between the core and an external memory. A clock divider receives an internal clock signal and outputs a divided clock signal. The memory controller uses the divided clock signal to establish an interface communication frequency with the memory. A boot control logic circuit, connected to the clock divider, compares a check data pattern to a predefined data pattern read from the memory by the memory controller at the interface frequency. When the predefined and check data patterns do not match, the boot control logic circuit instructs the clock divider to adjust the divided clock signal to change the interface frequency, after which the predefined data pattern reading and comparison are repeated, and when the predefined and check data patterns match, the memory controller reads a boot program, executed by the core, from the memory at the interface frequency.
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