VIDEO PROCESSING CIRCUIT AND ASSOCIATED VIDEO PROCESSING METHOD

    公开(公告)号:US20240119966A1

    公开(公告)日:2024-04-11

    申请号:US18182517

    申请日:2023-03-13

    发明人: Xiao-Ding ZHU

    IPC分类号: G11B20/10 G11B20/00

    摘要: The present invention discloses a video processing circuit, which is coupled to a memory chip and includes an image processing circuit. The image processing circuit includes a first channel, a second channel and a compression circuit. The two channels process first image data and second image data to generate first processed image data and second processed image data, respectively. The compression circuit compresses the first processed image data and the second processed image data to generate first compressed image data and second compressed image data, respectively. A memory block in the memory chip is configured as a ring buffer shared by the first channel and the second channel so as to store the first compressed image data and the second compressed image data.

    Encoding and decoding selectively retrievable representations of video content

    公开(公告)号:US09961355B2

    公开(公告)日:2018-05-01

    申请号:US15288836

    申请日:2016-10-07

    申请人: GoPro, Inc.

    摘要: A system and method disposed to enable encoding, decoding and manipulation of digital video with substantially less processing load than would otherwise required. In particular, one disclosed method is directed to generating a compressed video data structure that is selectively decodable to a plurality of resolutions including the full resolution of the uncompressed stream. The desired number of data components and the content of the data components that make up the compressed video data, which determine the available video resolutions, are variable based upon the processing carried out and the resources available to decode and process the data components. During decoding, efficiency is substantially improved because only the data components necessary to generate a desired resolution are decoded. In variations, both temporal and spatial decoding are utilized to reduce frame rates, and hence, further reduce processor load. The system and method are particularly useful for real-time video editing applications.