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公开(公告)号:US12224240B2
公开(公告)日:2025-02-11
申请号:US17396939
申请日:2021-08-09
Applicant: Micron Technology, Inc.
Inventor: S M Istiaque Hossain , Indra V. Chary , Anilkumar Chandolu , Sidhartha Gupta , Shuangqiang Luo
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H01L23/532 , H10B41/20 , H10B41/35 , H10B43/20 , H10B43/35
Abstract: A microelectronic device, including a stack structure including alternating conductive structures and dielectric structures is disclosed. Memory pillars extend through the stack structure. Contacts are laterally adjacent to the memory pillars and extending through the stack structure. The contacts including active contacts and support contacts. The active contacts including a liner and a conductive material. The support contacts including the liner and a dielectric material. The conductive material of the active contacts is in electrical communication with the memory pillars. Methods and electronic systems are also disclosed.
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公开(公告)号:US12191254B2
公开(公告)日:2025-01-07
申请号:US17453041
申请日:2021-11-01
Applicant: Micron Technology, Inc.
Inventor: Sidhartha Gupta , Anilkumar Chandolu
IPC: H01L23/528 , H01L21/768 , H01L23/532 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , G11C16/04
Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.
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公开(公告)号:US20240074201A1
公开(公告)日:2024-02-29
申请号:US17893436
申请日:2022-08-23
Applicant: Micron Technology, Inc.
Inventor: Matthew J. King , Albert Fayrushin , Sidhartha Gupta , Jun Fujiki , Masashi Yoshida , Yiping Wang , Taehyun Kim , Arun Kumar Dhayalan
IPC: H01L27/1157 , H01L27/11524 , H01L27/11556 , H01L27/11582
CPC classification number: H01L27/1157 , H01L27/11524 , H01L27/11556 , H01L27/11582
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. Conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. Individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. Upper channel-material strings of select-gate transistors are formed directly above the stack. Individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. Other embodiments, including structure, are disclosed.
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公开(公告)号:US11856763B2
公开(公告)日:2023-12-26
申请号:US17205954
申请日:2021-03-18
Applicant: Micron Technology, Inc.
Inventor: Lifang Xu , Sidhartha Gupta , Kar Wui Thong , Harsh Narendrakumar Jain
CPC classification number: H10B41/27 , G11C5/06 , H01L29/66666 , H01L29/7827 , H10B43/27
Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.
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公开(公告)号:US11849581B2
公开(公告)日:2023-12-19
申请号:US17064092
申请日:2020-10-06
Applicant: Micron Technology, Inc.
Inventor: Sidhartha Gupta , Anilkumar Chandolu , S M Istiaque Hossain
IPC: H01L21/768 , H10B43/27 , G11C11/56
CPC classification number: H10B43/27 , G11C11/5671 , H01L21/76879 , H01L21/76897
Abstract: An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.
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公开(公告)号:US20230139457A1
公开(公告)日:2023-05-04
申请号:US17453041
申请日:2021-11-01
Applicant: Micron Technology, Inc.
Inventor: Sidhartha Gupta , Anilkumar Chandolu
IPC: H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L23/532 , H01L21/768
Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.
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公开(公告)号:US20220238431A1
公开(公告)日:2022-07-28
申请号:US17161313
申请日:2021-01-28
Applicant: Micron Technology, Inc.
Inventor: Naveen Kaushik , Sidhartha Gupta , Pankaj Sharma , Haitao Liu
IPC: H01L23/522 , H01L27/11582 , G11C5/06 , H01L27/11556 , H01L21/768 , H01L21/48
Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号:US20250140691A1
公开(公告)日:2025-05-01
申请号:US19008496
申请日:2025-01-02
Applicant: Micron Technology, Inc.
Inventor: Sidhartha Gupta , Anilkumar Chandolu
IPC: H01L23/528 , G11C16/04 , H01L21/768 , H01L23/532 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.
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公开(公告)号:US12267997B2
公开(公告)日:2025-04-01
申请号:US18394273
申请日:2023-12-22
Applicant: Micron Technology, Inc.
Inventor: Lifang Xu , Sidhartha Gupta , Kar Wui Thong , Harsh Narendrakumar Jain
Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.
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公开(公告)号:US20240099007A1
公开(公告)日:2024-03-21
申请号:US18525652
申请日:2023-11-30
Applicant: Micron Technology, Inc.
Inventor: Yoshiaki Fukuzumi , Jun Fujiki , Matthew J. King , Sidhartha Gupta , Paolo Tessariol , Kunal Shrotri , Kye Hyun Baek , Kyle A. Ritter , Shuji Tanaka , Umberto Maria Meotto , Richard J. Hill , Matthew Holland
Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically overlying the strings of memory cells, and additional slot structures comprising a dielectric material extending through at least a portion of the additional stack structure and sub-dividing each of the block structures into sub-block structures, the additional slot structures horizontally neighboring the first pillars. Related microelectronic devices, electronic systems, and methods are also described.
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