公开(公告)号：US20150222301A1

公开(公告)日：2015-08-06

申请号：US14561189

申请日：2014-12-04

申请人： Samsung Electronics Co., Ltd.

发明人： Aram MARTIROSYAN ,  Jong-Shin SHIN

IPC分类号： H04B1/04 ,  H04B1/40

CPC分类号： H04B1/0475 ,  H03F3/2171 ,  H03F3/245 ,  H03F3/45139 ,  H03F2203/45481 ,  H04B1/40

摘要： A transmitting circuit includes a positive differential node, a negative differential node, a voltage mode driver, and a current mode driver. The voltage mode driver generates a first positive differential signal and a first negative differential signal. The voltage mode driver provides the first positive differential signal to the positive differential node and provides the first negative differential signal to the negative differential node. The current mode driver generates a second positive differential signal and a second negative differential signal. The current mode driver provides the second positive differential signal to the positive differential node and provides the second negative differential signal to the negative differential node. A differential signal voltage swing width between the positive differential node and the negative differential node is based at least on the operational state of the current mode driver and/or the voltage mode driver.

摘要翻译： 发送电路包括正差分节点，负差分节点，电压模式驱动器和当前模式驱动器。 电压模式驱动器产生第一正差分信号和第一负差分信号。 电压模式驱动器将第一正差分信号提供给正差分节点，并将第一负差分信号提供给负差分节点。 电流模式驱动器产生第二正差分信号和第二负差分信号。 电流模式驱动器向正差分节点提供第二正差分信号，并将第二负差分信号提供给负差分节点。 至少在当前模式驱动器和/或电压模式驱动器的操作状态下，正差动节点和负差动节点之间的差分信号电压摆幅宽度是至关重要的。

公开(公告)号：US4229705A

公开(公告)日：1980-10-21

申请号：US936905

申请日：1978-08-25

申请人： Susumu Takahashi ,  Tadaaki Chikashige

发明人： Susumu Takahashi ,  Tadaaki Chikashige

IPC分类号： H03F3/20 ,  H03F3/30 ,  H03F3/45 ,  H03F3/04

CPC分类号： H03F3/45139 ,  H03F3/3077 ,  H03F3/3081 ,  H03F3/45143 ,  H03F2203/45392 ,  H03F2203/45566 ,  H03F2203/45578 ,  H03F2203/45582 ,  H03F2203/45702

摘要： A differential amplifier able to produce differential-mode output signals different from one another in DC voltage level, is formed by connecting a pair of NPN transistors and another pair of PNP transistors so that the emitter electrodes of these four transistors are coupled to one another by a resistive coupling circuit. The resistive coupling circuit is so arranged that the resistance between the emitter electrodes of the NPN transistors is equal to that between the emitter electrodes of the PNP transistors, with the resistances between the emitter electrodes of one of the NPN transistors and of one of the PNP transistors being equal to that between the emitter electrodes of the other NPN transistor and the other PNP transistor. When one of two input signals is applied to the base electrodes of one of the NPN transistors and of one of the PNP transistors, with the other of the input signals applied to the base electrodes of the other NPN and PNP transistors, differential-mode output signals are obtained at the collector electrodes of the NPN transistors and differential-mode output signals of a different DC voltage level are obtained at the collector electrodes of the PNP transistors.

摘要翻译： 通过连接一对NPN晶体管和另一对PNP晶体管，可以通过连接一对PNP晶体管来形成能够产生直流电压电平彼此不同的差分模式输出信号的差分放大器，以使这四个晶体管的发射极彼此耦合。 电阻耦合电路。 电阻耦合电路被布置成使得NPN晶体管的发射极之间的电阻等于PNP晶体管的发射极之间的电阻，其中NPN晶体管之一的发射极之间的电阻和PNP晶体管之一之间的电阻 晶体管等于另一个NPN晶体管的发射极和另一个PNP晶体管之间的晶体管。 当两个输入信号中的一个被施加到NPN晶体管中的一个和PNP晶体管中的一个的基极时，另一个输入信号施加到另一个NPN和PNP晶体管的基极，差模输出 在NPN晶体管的集电极处获得信号，并且在PNP晶体管的集电极处获得不同DC电压电平的差模输出信号。

公开(公告)号：US3497824A

公开(公告)日：1970-02-24

申请号：US3497824D

申请日：1967-08-18

申请人： BELL TELEPHONE LABOR INC

发明人： GOORDMAN ROBERT V

IPC分类号： H03F3/45 ,  H03F3/68

CPC分类号： H03F3/4556 ,  H03F3/45085 ,  H03F3/45139 ,  H03F2203/45401 ,  H03F2203/45594 ,  H03F2203/45702

公开(公告)号：US20030184386A1

公开(公告)日：2003-10-02

申请号：US10306212

申请日：2002-11-27

申请人： Texas Instruments Incorporated

发明人： Alan L. Varner ,  Ahmad Dashtestani ,  Joel M. Halbert ,  Michael A. Steffes

IPC分类号： H03F001/38

CPC分类号： H03F3/45112 ,  H03F3/45139 ,  H03F3/45174

摘要： A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a closed-loop input buffer. An exemplary input buffer comprises a closed-loop current feedback amplifier configured within the overall current feedback amplifier, wherein the output of the input buffer corresponds to the inverting node of the overall current feedback amplifier. The closed-loop configuration of the input buffer is facilitated by the use of an internal feedback resistor coupled from an inverting input terminal of the input buffer to the output of the input buffer, which corresponds to the inverting input terminal of the overall current feedback amplifier. The closed-loop input buffer realizes a low output impedance since the loop gain reduces the output impedance of the input buffer. With a lower output impedance, the bandwidth of the current feedback amplifier becomes more independent of the gain, even at low current implementations. 1 Title:LOW POWER CURRENT FEEDBACK AMPLIFIER Inventor:Alan L. Varner Ahmad Dashtestani Joel M. Halbert Michael A. Steffes

摘要翻译： 提供具有较低输出阻抗输入级的低功率电流反馈放大器。 为了减小输出阻抗，输入级包括闭环输入缓冲器。 示例性输入缓冲器包括配置在总电流反馈放大器内的闭环电流反馈放大器，其中输入缓冲器的输出对应于整个电流反馈放大器的反相节点。 输入缓冲器的闭环配置通过使用从输入缓冲器的反相输入端耦合到输入缓冲器的输出的内部反馈电阻来实现，其对应于整个电流反馈放大器的反相输入端 。 闭环输入缓冲器实现了低输出阻抗，因为环路增益降低了输入缓冲器的输出阻抗。 具有较低的输出阻抗，即使在低电流实现下，电流反馈放大器的带宽变得更加独立于增益。

公开(公告)号：US06429744B2

公开(公告)日：2002-08-06

申请号：US09904806

申请日：2001-07-13

申请人： Kenneth W. Murray ,  Joel M. Halbert

发明人： Kenneth W. Murray ,  Joel M. Halbert

IPC分类号： H03F326

CPC分类号： H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

摘要： A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

摘要翻译： 根据本发明的偏轨缓冲电路和方法克服了现有技术的许多缺点。 用于提供参考信号的偏置轨缓冲电路被适当地配置为吸收出现在输出参考信号上的外部干扰。 用于吸收出现在输出参考信号处的外部干扰的方法适当地包括使用互补晶体管来根据外部干扰是否对输出参考信号提供减小或增加而将电流和电流吸收到所述输出参考信号 。 偏置轨缓冲电路适当地包括输入晶体管，第一对互补晶体管和第二对互补晶体管，使得第二对互补晶体管操作以源电流和吸收电流以吸收施加在所述输出参考信号上的外部干扰 。

公开(公告)号：US4357578A

公开(公告)日：1982-11-02

申请号：US190610

申请日：1980-09-25

申请人： Kenji Yokoyama

发明人： Kenji Yokoyama

IPC分类号： H03F3/30 ,  H03F3/45

CPC分类号： H03F3/3066 ,  H03F3/45112 ,  H03F3/45139 ,  H03F3/45165 ,  H03F2203/45392

摘要： A complementary differential amplifier comprises a first differential amplifier circuit having first conductivity type differential transistors and a second differential amplifier circuit having second conductivity type differential transistors. To improve a dynamic range and a slew rate of the complementary differential amplifier and, to prevent of the generation of TIM distortion with a simple construction, a constant voltage circuit is connected between commonly connected electrodes of differential transistors of the first differential amplifier circuit and commonly connected electrodes of differential transistors of the second differential amplifier circuit. To improve a slew rate in a high frequency range and to prevent the generation of TIM distortion, a capacitor may be connected between the commonly connected electrodes of the differential transistors of the first differential amplifier and the commonly connected electrodes of the differential transistors of the second differential amplifier.

摘要翻译： 互补差分放大器包括具有第一导电型差分晶体管的第一差分放大器电路和具有第二导电型差分晶体管的第二差分放大器电路。 为了提高互补差分放大器的动态范围和转换​​速率，为了防止以简单结构产生TIM失真，恒压电路连接在第一差分放大器电路的差分晶体管的共同连接的电极之间，并且通常 连接的第二差分放大器电路的差分晶体管的电极。 为了提高高频范围的转换速率并防止产生TIM失真，电容器可以连接在第一差分放大器的差分晶体管的公共连接的电极和第二差分放大器的差分晶体管的公共连接的电极之间 差分放大器。

公开(公告)号：US09748900B2

公开(公告)日：2017-08-29

申请号：US14983870

申请日：2015-12-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： En-Hsiang Yeh ,  An-Hsun Lo ,  Tzu-Jin Yeh

IPC分类号： H03F3/45 ,  H03F1/02 ,  H03F3/19

CPC分类号： H03F1/0205 ,  H03F3/19 ,  H03F3/45139 ,  H03F3/45183 ,  H03F2200/294 ,  H03F2200/451

摘要： A device is disclosed that includes a first gain stage and a first amplifier. The first gain stage is configured to generate a first signal according to a first input signal, and to multiply the first signal and the first input signal, to generate a second signal at a first output terminal, in which the first signal is associated with the even order signal components of the first input signal. The first amplifier is configured to amplify the first input signal to generate a third signal at the first output terminal, in order to output a first output signal with the first gain stage, in which the first output signal is the sum of the second signal and the third signal.

公开(公告)号：US20170194910A1

公开(公告)日：2017-07-06

申请号：US14983870

申请日：2015-12-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： En-Hsiang YEH ,  An-Hsun LO ,  Tzu-Jin YEH

IPC分类号： H03F1/02 ,  H03F3/19

CPC分类号： H03F1/0205 ,  H03F3/19 ,  H03F3/45139 ,  H03F3/45183 ,  H03F2200/294 ,  H03F2200/451

摘要： A device is disclosed that includes a first gain stage and a first amplifier. The first gain stage is configured to generate a first signal according to a first input signal, and to multiply the first signal and the first input signal, to generate a second signal at a first output terminal, in which the first signal is associated with the even order signal components of the first input signal. The first amplifier is configured to amplify the first input signal to generate a third signal at the first output terminal, in order to output a first output signal with the first gain stage, in which the first output signal is the sum of the second signal and the third signal.

公开(公告)号：US06297699B1

公开(公告)日：2001-10-02

申请号：US09692017

申请日：2000-10-19

申请人： Kenneth W. Murray ,  Joel M. Halbert

发明人： Kenneth W. Murray ,  Joel M. Halbert

IPC分类号： H03F326

CPC分类号： H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

摘要： A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

摘要翻译： 根据本发明的偏轨缓冲电路和方法克服了现有技术的许多缺点。 用于提供参考信号的偏置轨缓冲电路被适当地配置为吸收出现在输出参考信号上的外部干扰。 用于吸收出现在输出参考信号处的外部干扰的方法适当地包括使用互补晶体管来根据外部干扰是否对输出参考信号提供减小或增加而将电流和电流吸收到所述输出参考信号 。 偏置轨缓冲电路适当地包括输入晶体管，第一对互补晶体管和第二对互补晶体管，使得第二对互补晶体管操作以源电流和吸收电流以吸收施加在所述输出参考信号上的外部干扰 。

公开(公告)号：US6163216A

公开(公告)日：2000-12-19

申请号：US215402

申请日：1998-12-18

申请人： Kenneth W. Murray ,  Joel M. Halbert

发明人： Kenneth W. Murray ,  Joel M. Halbert

IPC分类号： H03F3/30 ,  H03F3/343 ,  H03F3/45

CPC分类号： H03F3/3079 ,  H03F3/3066 ,  H03F3/3076 ,  H03F3/3081 ,  H03F3/343 ,  H03F3/45139 ,  H03F3/45152 ,  H03F3/45475 ,  H03F3/45502 ,  H03F3/4556 ,  H03F3/456 ,  H03F3/45609 ,  H03F3/45937

摘要： A wideband operational amplifier in accordance with the present invention overcomes many shortcomings of the prior art. A wideband operational amplifier may be configured to provide a high output voltage and high output current. The amplifier may comprise an input stage having a first input buffer and a second input buffer, and an output stage amplifier having an output buffer. The input stage may also include current mirrors configured to facilitate a lower input offset voltage and lower input voltage noise. Moreover, the operational amplifier may also provide a wide common-mode input range and full power bandwidth simultaneously.

摘要翻译： 根据本发明的宽带运算放大器克服了现有技术的许多缺点。 宽带运算放大器可以被配置为提供高输出电压和高输出电流。 放大器可以包括具有第一输入缓冲器和第二输入缓冲器的输入级，以及具有输出缓冲器的输出级放大器。 输入级还可以包括配置成便于较低输入偏移电压和较低输入电压噪声的电流镜。 此外，运算放大器还可以同时提供宽的共模输入范围和全功率带宽。