公开(公告)号：US20210013195A1

公开(公告)日：2021-01-14

申请号：US16874536

申请日：2020-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jun-De JIN ,  Tzu-Jin YEH

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a metal-oxide-semiconductor device, and a feature. The metal-oxide-semiconductor device is disposed in the substrate. The feature is disposed adjacent to the metal-oxide-semiconductor device. The feature extends into the substrate with a first depth and the metal-oxide-semiconductor device extends into the substrate with a second depth smaller than the first depth.

公开(公告)号：US20180131332A1

公开(公告)日：2018-05-10

申请号：US15344133

申请日：2016-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Hsun LO ,  Wen-Sheng CHEN ,  En-Hsiang YEH ,  Tzu-Jin YEH

IPC: H03F1/34 ,  H03F3/193 ,  H03F1/56 ,  H03F3/45

CPC classification number: H03F1/342 ,  H03F1/565 ,  H03F3/193 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45018 ,  H03F2203/45306

Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first trans conductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.

公开(公告)号：US20160204191A1

公开(公告)日：2016-07-14

申请号：US15075759

申请日：2016-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Ta LU ,  Chi-Hsien LIN ,  Hsien-Yuan LIAO ,  Ho-Hsiang CHEN ,  Tzu-Jin YEH

IPC: H01L49/02

CPC classification number: H01L28/88 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.

Abstract translation: 公开了通常包括同心电容器的同心电容器结构。 每个同心电容器包括形成在衬底的第一层上的第一多个周边板和形成在衬底的第二层上的第二多个周边板。 第一多个周边板沿第一方向延伸，第二多个周边板沿与第一方向不同的第二方向延伸。 第一组第一组多个周边板电耦合到第一组第二多个周边板，第二组第一组周边板电耦合到第二组第二组周边板。 在第一层中形成多个电容性交叉板，使得每个交叉板与第二多个周边板中的至少两个重叠。

公开(公告)号：US20240371859A1

公开(公告)日：2024-11-07

申请号：US18773203

申请日：2024-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jun-De JIN ,  Tzu-Jin YEH

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.

公开(公告)号：US20240088842A1

公开(公告)日：2024-03-14

申请号：US18513103

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Garming LIANG ,  Simon CHAI ,  Tzu-Jin YEH ,  En-Hsiang YEH ,  Wen-Sheng CHEN

IPC: H03F3/21 ,  H01L27/06 ,  H01L27/092 ,  H03F1/02

CPC classification number: H03F3/211 ,  H01L27/0629 ,  H01L27/0928 ,  H03F1/0205 ,  H03F1/223

Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

公开(公告)号：US20220336446A1

公开(公告)日：2022-10-20

申请号：US17853596

申请日：2022-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jun-De JIN ,  Tzu-Jin YEH

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.

公开(公告)号：US20230112936A1

公开(公告)日：2023-04-13

申请号：US18081513

申请日：2022-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.,

Inventor： Garming LIANG ,  Simon CHAI ,  Tzu-Jin YEH ,  En-Hsiang YEH ,  Wen-Sheng CHEN

IPC: H03F3/21 ,  H01L27/06 ,  H01L27/092 ,  H03F1/02

Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

公开(公告)号：US20160358912A1

公开(公告)日：2016-12-08

申请号：US14732670

申请日：2015-06-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chung CHEN ,  Chi-Feng HUANG ,  Victor Chiang LIANG ,  Fu-Huan TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Han-Min TSAI ,  Hong-Lin CHU

IPC: H01L27/088 ,  H01L21/265 ,  H03D7/14 ,  H01L21/266 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/167

CPC classification number: H03D7/1441 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785 ,  H03D7/1458

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract translation: 提供一种制造包括上通道注入晶体管的半导体器件的方法。 该方法包括形成在衬底上沿第一方向延伸的一个或多个翅片。 一个或多个翅片包括沿第一方向的第一区域和沿着第一方向的第一区域两侧的第二区域。 掺杂剂浅地植入翅片的第一区域的上部，而不是在翅片的第一区域的第二区域中而不是在下部。 形成在垂直于第一方向的第二方向上延伸的栅极结构，覆盖鳍片的第一区域，并且形成覆盖翅片的第二区域的源极/漏极，从而形成上沟道注入晶体管。

公开(公告)号：US20150249051A1

公开(公告)日：2015-09-03

申请号：US14712940

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming Hsien TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Sa-Lly LIU ,  Fu-Lung HSUEH

IPC: H01L23/522 ,  H03F1/26 ,  H01L23/58 ,  H03F3/04 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/645 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/092 ,  H01L28/10 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2924/0002 ,  H03F1/26 ,  H03F3/04 ,  H03F2200/294 ,  H03F2200/372 ,  H01L2924/00

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract translation: 三维（3D）电路包括包括半导体衬底的第一层，与第一层相邻设置的第二层，包括电感元件部分的三维电感器，电感元件部分包括从第一层延伸到 第二层的介电层。 3D电路包括围绕导电通孔的至少一部分的接地屏蔽。 在一些实施例中，接地屏蔽包括中空圆柱形笼。 在一些实施例中，3D电路是低噪声放大器。

公开(公告)号：US20240312982A1

公开(公告)日：2024-09-19

申请号：US18669378

申请日：2024-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jun-De JIN ,  Tzu-Jin YEH

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0629 ,  H01L29/0653 ,  H01L29/4238

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.