公开(公告)号：US20040222445A1

公开(公告)日：2004-11-11

申请号：US10864232

申请日：2004-06-09

发明人： Stephen J. Hudgens ,  Tyler A. Lowrey

IPC分类号： H01L027/148 ,  H01L029/768

CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. The resistivity of the contact is modified by at least one of implanting ions into the contact, depositing a material on the contact, and treating the contact with plasma. In an aspect, a spacer is formed within the opening and programmable material is formed within the opening and on the modified contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

摘要翻译： 在一方面，提供一种设置和重新编程可编程设备的状态的设备。 在一方面，提供一种方法，使得通过暴露形成在基底上的接触的电介质形成开口。 接触的电阻率通过将离子注入到接触中的至少一种来修饰，在接触上沉积材料，以及处理与等离子体的接触。 在一个方面，在开口内形成间隔件，并且在开口内和修改的接触件上形成可编程材料。 导体形成在可编程材料上，触点传输到信号线。

公开(公告)号：US20040195597A1

公开(公告)日：2004-10-07

申请号：US10826120

申请日：2004-04-15

申请人： Astralux, Inc.

发明人： John Tarje Torvik ,  Jacques Isaac Pankove

IPC分类号： H01L029/768

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/7378

摘要： A bipolar transistor includes a collector that is selected from the group SiC and SiC polytypes (4H, 6H, 15R, 3C . . . ), a base that is selected from the group Si, Ge and SiGe, at least a first emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, amorphous-SiC and diamond-like carbon, and at least a second emitter that is selected from the group Si, SiGe, SiC, amorphous-Si, amorphous-SiC and diamond-like carbon. Direct-wafer-bonding is used to assemble the bipolar transistor. In an embodiment the bandgap of the collector, the bandgap of the at least a first emitter and the bandgap of the at least a second emitter are larger than the bandgap of the base.

摘要翻译： 双极晶体管包括选自SiC和SiC多型（4H，6H，15R，3C ...）的集电体，其选自Si，Ge和SiGe族，至少第一发射极为 选自Si，SiGe，SiC，非晶Si，非晶SiC和类金刚石碳，以及至少一个选自Si，SiGe，SiC，非晶Si，非晶SiC和金刚石的第二发射极 类碳。 直接晶片接合用于组装双极晶体管。 在一个实施例中，集电极的带隙，至少第一发射极的带隙和至少第二发射极的带隙大于基极的带隙。

公开(公告)号：US20040129957A1

公开(公告)日：2004-07-08

申请号：US10715848

申请日：2003-11-19

发明人： Manabu Takahashi ,  Koji Kawamichi ,  Shohei Oishi ,  Masaru Kohara

IPC分类号： H01L029/768

CPC分类号： H02M1/38

摘要： In a semiconductor device for generating complementary PWM signals for, for example, controlling an inverter, a dead time is flexibly added by using a simple architecture. A dead time addition unit adds time elapsing until a value of a timer reaches a set value of a register as a first dead time at a rise of a first PWM signal. On the other hand, time elapsing until the value of the timer reaches a set value of another register is added as a second dead time at a rise of a second PWM signal.

摘要翻译： 在用于产生用于例如控制逆变器的互补PWM信号的半导体器件中，通过使用简单的架构灵活地添加死区时间。 死区时间添加单元增加时间经过，直到定时器的值达到寄存器的设定值为第一个PWM信号上升的第一个死区时间。 另一方面，直到定时器的值达到另一个寄存器的设定值为止的时间在第二个PWM信号的上升处被添加为第二死区时间。

公开(公告)号：US20040026718A1

公开(公告)日：2004-02-12

申请号：US10438865

申请日：2003-05-16

发明人： Eiichi Okamoto ,  Shunsuke Tanaka ,  Shinji Uya

IPC分类号： H01L047/00 ,  H01L027/148 ,  H01L029/768

CPC分类号： H01L27/14603 ,  H01L27/14612 ,  H01L27/14687 ,  H01L27/14806

摘要： In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.

摘要翻译： 在形成在半导体衬底上的光电转换部分和靠近光电转换部分的电荷耦合器件（CCD）的传输路径的栅氧化膜的固态图像拾取装置中， 包含氧化硅膜（SiO）和氮化硅膜（SiN）的层压膜，气体氧化膜具有单层结构，其中栅极氧化膜的光电转换部分侧的至少一端不含有硅 氮化膜。

公开(公告)号：US20040000679A1

公开(公告)日：2004-01-01

申请号：US10180046

申请日：2002-06-27

申请人： Matrix Semiconductor, Inc.

发明人： Kedar Patel ,  Alper Ilkbahar ,  Roy Scheuerlein ,  Andrew J. Walker

IPC分类号： H01L029/76 ,  H01L027/148 ,  H01L029/768

CPC分类号： H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052

摘要： A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

摘要翻译： 半导体器件包括两个晶体管，其中一个晶体管的栅电极和另一个晶体管的源极或漏极位于同一导轨中。 单片三维阵列包含多个这样的装置。 阵列的不同级别的晶体管优选地具有不同的取向。

公开(公告)号：US20030178652A1

公开(公告)日：2003-09-25

申请号：US10134223

申请日：2002-04-25

发明人： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L027/148 ,  H01L029/768 ,  H01L027/108 ,  H01L029/76 ,  H01L029/94

CPC分类号： H01L29/792 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L29/66833

摘要： A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

摘要翻译： 一种非易失性只读存储器件，其中字线在衬底上，字线包括金属层多晶硅线。 捕获层还位于字线和基板之间。 多晶硅保护线形成在衬底上，多晶硅保护线连接字线和衬底中的接地掺杂区，其中多晶硅保护线的电阻高于字线的电阻。

公开(公告)号：US20030153113A1

公开(公告)日：2003-08-14

申请号：US10292773

申请日：2002-11-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY

发明人： Chien-Ling Chan

IPC分类号： H01L021/00 ,  H01L029/768 ,  H01L031/062

CPC分类号： H01L27/14609 ,  H01L27/1463

摘要： A method is disclosed for forming an image sensor. In a semiconductor wafer containing a p-type region an n-type connection region is formed within the p-type region. An n-type photodiode region is formed in the p-type region connected to the connection region. A field oxide isolation region is formed, having a part that is over portions of the n-type connection region and the n-type photodiode region. This part of the field oxide region covers the area where these regions are connected and extends into these regions. The edges of this part of the field oxide region fall within these regions, while leaving a distance between these edges and pn junctions formed by the connection region and the p-type region and the n-type photodiode region and p-type region. A gate oxide is formed over regions not covered by field oxide. An extended gate structure is formed extending from above this part of the field oxide isolation region to a distance beyond the connection region so as to accommodate a channel of an n-channel MOSFET. The drain region of the n-channel MOSFET is formed, with the connection region acting as the source. A blanket transparent insulating layer is deposited.

摘要翻译： 公开了一种用于形成图像传感器的方法。 在包含p型区域的半导体晶片中，在p型区域内形成有n型连接区域。 在与连接区域连接的p型区域中形成n型光电二极管区域。 形成具有在n型连接区域和n型光电二极管区域的部分之上的部分的场氧化物隔离区域。 场氧化物区域的这一部分覆盖这些区域连接并延伸到这些区域中的区域。 场氧化物区域的这些部分的边缘落在这些区域内，同时留下这些边缘与由连接区域和p型区域以及n型光电二极管区域和p型区域形成的pn结之间的距离。 在不被场氧化物覆盖的区域上形成栅极氧化物。 扩展的栅极结构从场氧化物隔离区的该部分的上方延伸到超出连接区的距离，以便容纳n沟道MOSFET的沟道。 形成n沟道MOSFET的漏极区域，其中连接区域用作源极。 沉积一层覆盖的透明绝缘层。

公开(公告)号：US20030139011A1

公开(公告)日：2003-07-24

申请号：US10254878

申请日：2002-09-26

申请人： Matrix Semiconductor, Inc.

发明人： James M. Cleeves ,  Vivek Subramanian

IPC分类号： H01L021/336 ,  H01L021/3205 ,  H01L029/768

CPC分类号： H01L27/11568 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2211/5611 ,  G11C2211/5612 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface. According to the second aspect of the present invention, a transistor is provided that has a source, a channel, a drain, and a plurality of gates where the channel current flows vertically between the source and drain. According to a third embodiment of the present invention, a memory element is formed using a transistor that has a read current that flows in a direction perpendicular to a substrate in or over which the transistors form. The transistor has a charge storage medium for storing its state. Multiple control gates address the transistor.

摘要翻译： 本发明是一种多位非易失性存储器及其制造方法。 根据本发明，形成具有第一和第二通道表面的硅通道体。 在第一通道表面附近形成电荷存储介质，并且在第二通道表面附近形成第二电荷存储介质。 与第一通道表面相邻的第一电荷存储介质相邻地形成第一控制栅极，并且邻近第二表面邻近第二电荷存储介质形成第二控制栅极。 根据本发明的第二方面，提供一种具有源极，沟道，漏极和多个栅极的晶体管，其中沟道电流在源极和漏极之间垂直流动。 根据本发明的第三实施例，使用晶体管形成存储元件，该晶体管具有在垂直于晶体管形成的晶体管或其上的衬底的方向上流动的读取电流。 晶体管具有用于存储其状态的电荷存储介质。 多个控制门寻址晶体管。

公开(公告)号：US20030020100A1

公开(公告)日：2003-01-30

申请号：US10236826

申请日：2002-09-06

发明人： Robert M. Guidash

IPC分类号： H01L029/768 ,  H01L021/00

CPC分类号： H04N5/3575 ,  H04N5/35554 ,  H04N5/3594 ,  H04N5/3742 ,  H04N5/378

摘要： A X-Y addressable MOS imager sensor method and apparatus wherein a semiconductor based MOS sensor having an array of pixels forming the X-Y addressable MOS imager, the X-Y addressable MOS imager having a plurality of the pixels such that each pixel within the plurality of pixels has a photodetector with a reset mechanism that adjusts the photodetector potential to a predetermined potential level employs the measuring a plurality of reset levels with two different elapsed times between reset and measurement of the reset level, a comparison circuit operatively coupled to the means for measuring to determine a difference in reset levels, a predetermined set of transfer functions used to identify effective signal levels of the photodetectors, and determines from the difference which transfer function is applicable to that photodetector range of accumulated light. In response to the difference detected, transfer functions are applied to the charge read out from the photodetector. The transfer functions comprise a first transfer function that is pre-photodetector saturation function and a second transfer function that is a post-photodetector saturation transfer function. These transfer functions are applied to two reset levels of the photodetector within the same row readout period. The response to the difference can be the application of a series of digital adds and digital multiplies. The difference between the 2 reset levels is used to calculate the effective pixel signal level from the difference.

公开(公告)号：US20020175350A1

公开(公告)日：2002-11-28

申请号：US10055343

申请日：2002-01-22

发明人： Jan Theodoor Jozef Bosiers ,  Agnes Catharina Maria Kleimann ,  Yvonne Astrid Boersma

IPC分类号： H01L027/148 ,  H01L029/768 ,  H01L031/113

CPC分类号： H01L29/76816 ,  H01L27/148

摘要： The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.

摘要翻译： 本发明涉及一种埋入通道型的CCD，其包括形成第一导电类型的区域（12）形式的电荷传输通道，例如n型，在相反电导率的阱（13）中 类型，在示例中为p型。 为了获得在一个或多个栅极（9,10a）下方的通道中的漂移场以改善电荷转移，阱具有掺杂分布，使得平均浓度在电荷传输方向上减小。 这样的形状可以通过用掩模在阱注入期间覆盖阱的区域来形成，从而在栅极（9,10a）下面比在通道的其它部分下方注入更少的离子。 根据本发明，可以产生组合比较大长度的门（10a），例如在输出门（9）前面的输出级中以高传输速率获得足够的存储容量。