公开(公告)号：US06351024B1

公开(公告)日：2002-02-26

申请号：US09245207

申请日：1999-02-05

申请人： Martin Ruff ,  Hans-Joachim Schulze

发明人： Martin Ruff ,  Hans-Joachim Schulze

IPC分类号： H01L2936

CPC分类号： H01L29/0661 ,  H01L29/32 ,  H01L29/861

摘要： A semiconductor body including a first surface, a second surface, and a base doping for electrical conductivity. A first doped region is on the first surface and a second doped is on the second surface. The two doped regions are doped with opposites signs for electrical conductivity. A contact is positioned on each of the two doped regions. Another region is within the semiconductor body and has an outer section in which the charge carrier concentration in the outer section is lower due to the reduction of the concentration of dopant in the first doped region and/or the increase of concentration of recombination centers in the outer section.

摘要翻译： 一种半导体本体，包括第一表面，第二表面和用于导电性的基底掺杂。 第一掺杂区域在第一表面上，第二掺杂区域位于第二表面上。 两个掺杂区域掺杂有相反的电导率符号。 接触位于两个掺杂区域中的每一个上。 另一区域在半导体本体内，并且具有外部部分，其中由于第一掺杂区域中的掺杂剂的浓度的降低和/或在第二掺杂区域中的复合中心的浓度的增加，外部部分中的载流子浓度较低 外部部分。

公开(公告)号：US06667522B2

公开(公告)日：2003-12-23

申请号：US10155632

申请日：2002-05-23

申请人： Kramadhati V. Ravi ,  Li Ling ,  Sing-Chung S. Hu

发明人： Kramadhati V. Ravi ,  Li Ling ,  Sing-Chung S. Hu

IPC分类号： H01L2936

CPC分类号： H01L27/0921 ,  C30B15/00 ,  C30B29/06 ,  C30B33/00 ,  H01L21/223 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/105 ,  Y10S148/041

摘要： Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circuits or other devices may include a semiconductor wafer with a substantially uniformly boron-doped bulk region and a reduced boron concentration layer near a surface of the wafer. An electrical circuit element may be provided in the reduced boron concentration layer.

摘要翻译： 技术包括加热基本上均匀的硼掺杂晶片以在晶片的近表面区域中实现显着增加的电阻率，并在近表面区域中形成至少一个电路元件。 集成电路或其他器件可以包括具有基本上均匀的硼掺杂体区域和靠近晶片表面的还原硼浓度层的半导体晶片。 还可以在还原硼浓度层中设置电路元件。

公开(公告)号：US06433400B1

公开(公告)日：2002-08-13

申请号：US09153753

申请日：1998-09-15

申请人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

发明人： Mark I. Gardner ,  H. Jim Fulford ,  Derick J. Wristers

IPC分类号： H01L2936

CPC分类号： H01L21/02233 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/31612 ,  H01L21/76237

摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure. The masking layer may prevent the barrier atoms from being incorporated into any other regions of the substrate.

摘要翻译： 一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。 该方法包括在半导体衬底上形成电介质掩模层。 然后通过掩模层形成开口。 在开口内的掩模层的侧壁上形成一对电介质隔离物。 然后在电介质间隔物之间​​的半导体衬底中蚀刻沟槽。 然后在沟槽的壁和基底上热生长第一介电层。 将CVD氧化物沉积到沟槽中并进行处理，使得CVD氧化物的上表面与衬底表面相当。 间隔物的一部分也被去除，使得间隔物的厚度在约0至200埃之间。 然后将半导体形貌暴露于阻挡夹带气体并加热，使得势垒原子并入到紧邻沟槽隔离结构的有源区域的区域中。 掩模层可以防止阻挡原子被结合到衬底的任何其它区域中。

公开(公告)号：US06791121B2

公开(公告)日：2004-09-14

申请号：US10083673

申请日：2002-02-25

申请人： Michio Nemoto ,  Akira Nishiura ,  Tatsuya Naito

发明人： Michio Nemoto ,  Akira Nishiura ,  Tatsuya Naito

IPC分类号： H01L2936

CPC分类号： H01L29/868 ,  H01L29/872

摘要： A semiconductor device, such as a pin diode, includes a first drift layer, a second drift layer, an anode layer on the first drift layer, and a buffer layer formed between the first and second drift layers. The shortest distance from the pn-junction between the anode layer and the buffer layer, and the thickness of the buffer layer are set at the respective values at which a high breakdown voltage is obtained, while reducing the tradeoff relation between the soft recovery and the fast and low-loss reverse recovery.

摘要翻译： 诸如pin二极管的半导体器件包括第一漂移层，第二漂移层，第一漂移层上的阳极层和形成在第一和第二漂移层之间的缓冲层。 将阳极层和缓冲层之间的pn结的最短距离和缓冲层的厚度设定为获得高击穿电压的各个值，同时降低软恢复与 快速和低损耗反向恢复。

公开(公告)号：US06700141B2

公开(公告)日：2004-03-02

申请号：US09978847

申请日：2001-10-17

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato

IPC分类号： H01L2936

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/7802

摘要： A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.

摘要翻译： 提供了可靠的超结半导体器件，其有助于放松导通电阻和击穿电压之间的折衷关系，并提高在感性负载下的雪崩耐受能力。 超结半导体器件包括在第一交替导电型层和n ++类漏极层之间包括薄的第一交替导电型层和重掺杂n +型中间漏极层的有源区，以及 包括厚的第二交替导电类型层的击穿耐受区域。 或者，有源区包括第一交替导电类型层和第n +型漏极之间的第一交变导电类型层和第三交变导电类型层，第三交变导电类型层比第一交变导电类型层更重掺杂 。