公开(公告)号：US06475864B1

公开(公告)日：2002-11-05

申请号：US09694098

申请日：2000-10-23

申请人： Takahiro Sato ,  Katsunori Ueno ,  Tatsuhiko Fujihira ,  Kenji Kunihara ,  Yasuhiko Onishi ,  Susumu Iwamoto

发明人： Takahiro Sato ,  Katsunori Ueno ,  Tatsuhiko Fujihira ,  Kenji Kunihara ,  Yasuhiko Onishi ,  Susumu Iwamoto

IPC分类号： H01L21336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/66712

摘要： A method of manufacturing reduces costs and provides an excellent mass-productivity, super-junction semiconductor device, which facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double difflusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, the oxide film is removed by ion etching, and trenches are dug. The p-type epitaxial layers are buried in the trenches by selective epitaxial growth, and the remaining oxide film is removed. The portions of n-type semiconductor substrate not etched off remain as n-type drift regions, resulting in an alternating conductivity type layer formed of n-type drift regions and p-type partition regions. A drain electrode is deposited on the back surface of alternating conductivity type layer.

摘要翻译： 一种制造方法降低了成本，并且提供了优异的大规模生产率的超结半导体器件，其有助于减少交替导电型层对象的热处理时间，并且防止交替导电型层的特性受到损害。 在p型基极区中包括p型基极区域，p +型接触区域，p型基极区域中的n +型源极区域，栅极电极层和源极电极的表面MOSFET结构形成在 通过通常的双重扩散MOSFET制造工艺，n型半导体衬底的表面部分。 在半导体衬底的背面通过CVD法沉积氧化膜，在氧化物膜上形成用于限定p型分隔区的抗蚀剂掩模，通过离子蚀刻去除氧化膜，并且挖出沟槽。 通过选择性外延生长将p型外延层埋入沟槽中，并除去剩余的氧化物膜。 未被蚀刻的n型半导体衬底的部分保持为n型漂移区，导致由n型漂移区和p型分隔区形成的交变导电型层。 在交替导电型层的背面上沉积漏电极。

公开(公告)号：US06674126B2

公开(公告)日：2004-01-06

申请号：US10073671

申请日：2002-02-11

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： A01L29772

CPC分类号： H01L29/7802 ,  H01L29/0634

摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。

公开(公告)号：US07042046B2

公开(公告)日：2006-05-09

申请号：US10925407

申请日：2004-08-25

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/76 ,  H01L23/58

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

公开(公告)号：US07002205B2

公开(公告)日：2006-02-21

申请号：US10735501

申请日：2003-12-12

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

公开(公告)号：US06903418B2

公开(公告)日：2005-06-07

申请号：US10678941

申请日：2003-10-03

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/772

CPC分类号： H01L29/7802 ,  H01L29/0634

摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。

公开(公告)号：US20050017292A1

公开(公告)日：2005-01-27

申请号：US10925407

申请日：2004-08-25

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L29/06 ,  H01L21/331 ,  H01L21/336 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

公开(公告)号：US06696728B2

公开(公告)日：2004-02-24

申请号：US10099449

申请日：2002-03-15

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7395 ,  H01L29/872

摘要： To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.

摘要翻译： 为了提供一种超级结MOSFET，大大降低了导通电阻和击穿电压之间的折衷关系，并具有外围结构，这有助于减小其截止状态下的漏电流并稳定其击穿电压。 根据本发明的垂直MOSFET包括包括第一交变导电类型层的漏极漂移区; 包括漏极漂移区周围的第二交变导电型层的击穿耐受区域（周边区域），层叠的上下方向延伸的n型区域形成的第二交替导电型层和层叠的上下方向延伸的p型区域 交替; 围绕第二交变导电类型层的n型区域; 以及形成在n型区域的表面部分中的p型区域，以减小MOSFET的截止状态下的漏电流。

公开(公告)号：US06693323B2

公开(公告)日：2004-02-17

申请号：US10237828

申请日：2002-09-09

申请人： Takahiro Sato ,  Katsunori Ueno ,  Tatsuhiko Fujihira ,  Kenji Kunihara ,  Yasuhiko Onishi ,  Susumu Iwamoto

发明人： Takahiro Sato ,  Katsunori Ueno ,  Tatsuhiko Fujihira ,  Kenji Kunihara ,  Yasuhiko Onishi ,  Susumu Iwamoto

IPC分类号： H01L27148

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/66712

摘要： A method of manufacture reduces costs and provides an excellent mass-productivity, a super-junction semiconductor device, that facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double diffusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, oxide film is removed by ion etching, and trenches are dug. The p-type epitaxial layers are buried in the trenches by selective epitaxial growth, and the remaining oxide film is removed. The portions of n-type semiconductor substrate not etched off remain as n-type drift regions, resulting in an alternating conductivity type layer formed of n-type drift regions and p-type partition regions. A drain electrode is deposited on the back surface of alternating conductivity type layer.

摘要翻译： 一种制造方法降低了成本并且提供了优异的大规模生产率的超结半导体器件，其有助于减少交替导电型层对象的热处理时间，并且防止交替导电型层的特性受到损害。 表面MOSFET结构，包括p型基极区域中的p型基极区域，p +型接触区域，p型基极区域中的n +型源极区域，栅电极层和源极 电极通过通常的双扩散MOSFET制造工艺形成在n型半导体衬底的表面部分中。 通过CVD法在半导体衬底的背面上沉积氧化膜，在氧化膜上形成用于限定p型分隔区的抗蚀剂掩模，通过离子蚀刻去除氧化膜，并且挖出沟槽。 通过选择性外延生长将p型外延层埋入沟槽中，并除去剩余的氧化物膜。 未被蚀刻的n型半导体衬底的部分保持为n型漂移区，导致由n型漂移区和p型分隔区形成的交变导电型层。 在交替导电型层的背面上沉积漏电极。

公开(公告)号：US06724042B2

公开(公告)日：2004-04-20

申请号：US09781066

申请日：2001-02-09

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Susumu Iwamoto ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.

摘要翻译： 公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。 优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域 区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。 由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和 半导体芯片耗尽。 因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

公开(公告)号：US06700141B2

公开(公告)日：2004-03-02

申请号：US09978847

申请日：2001-10-17

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato

IPC分类号： H01L2936

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/7802

摘要： A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.

摘要翻译： 提供了可靠的超结半导体器件，其有助于放松导通电阻和击穿电压之间的折衷关系，并提高在感性负载下的雪崩耐受能力。 超结半导体器件包括在第一交替导电型层和n ++类漏极层之间包括薄的第一交替导电型层和重掺杂n +型中间漏极层的有源区，以及 包括厚的第二交替导电类型层的击穿耐受区域。 或者，有源区包括第一交替导电类型层和第n +型漏极之间的第一交变导电类型层和第三交变导电类型层，第三交变导电类型层比第一交变导电类型层更重掺杂 。