公开(公告)号：US4489422A

公开(公告)日：1984-12-18

申请号：US332831

申请日：1981-12-21

申请人： Joseph P. Paradise ,  Donald J. Derkach

发明人： Joseph P. Paradise ,  Donald J. Derkach

IPC分类号： H03K21/14 ,  G06M3/12

CPC分类号： H03K21/14

摘要： A circuit for controlling the application of a timing pulse to a count down chain where the contents of the count down chain are read-out in stages and asynchronously with respect to the application of the timing pulse. The control circuit ensures that a timing pulse is not applied during the read-out of the contents of the count down chain.

摘要翻译： 用于控制定时脉冲应用于向下计数链的电路，其中计数下行链路的内容被分阶段地读出并且相对于定时脉冲的应用而异步读出。 控制电路确保在读出计数下行链路的内容期间不施加定时脉冲。

公开(公告)号：US10168435B2

公开(公告)日：2019-01-01

申请号：US15430894

申请日：2017-02-13

申请人： THERMO EBERLINE LLC

发明人： Greg Holger Nelson ,  Phillip Edward Beeson ,  Alan John Laing

IPC分类号： G01T1/15 ,  H03K3/012 ,  H03K21/14 ,  G01T1/17

摘要： A system includes a pulse counter having a selectable pulse counter read-out rate, a pulse counter read-out (PCRO) storage register that stores a PCRO count, and a pulse-burst counter that has a pulse-burst counter read-out rate that is faster than all but the fastest selectable pulse counter read-out rate, a subtractor module in electronic communication with the pulse counter and the PCRO that subtracts the PCRO count from the pulse counter read-out count to output an uncorrected pulse count, a selection module in electronic communication with the pulse-burst counter that selects the pulse counter read-out rate in response to input from the pulse-burst counter, a multiplexer in electronic communication with the subtractor module and the selection module, the multiplexer selecting from among at least two dead-time correction transforms, the transform corresponding to the selected pulse counter read-out rate, and a control-and-readout module that outputs a dead-time corrected pulse rate.

公开(公告)号：US4692641A

公开(公告)日：1987-09-08

申请号：US829707

申请日：1986-02-13

申请人： Frederick J. Highton

发明人： Frederick J. Highton

IPC分类号： H03M1/66 ,  H03K3/2885 ,  H03K3/289 ,  H03K19/018 ,  H03K19/0185 ,  H03M1/74 ,  H03M9/00 ,  H03K19/003 ,  H03K19/086 ,  H03K19/092 ,  H03K21/14

CPC分类号： H03K3/289 ,  H03K19/01812 ,  H03K19/018514 ,  H03K3/2885

摘要： A serial-to-parallel converter receiving a clock signal and continuous serial stream of input data, each having TTL logic levels, produces parallel outputs for driving current switches of a digital-to-analog converter (DAC). The data and clock signals each are converted to ECL logic levels by a pair of emitter-coupled differential lateral PNP transistors having their collectors coupled to a pair of NPN current mirror circuits, the outputs of which drive the bases and emitters of a pair of NPN emitter follower transistors, resulting in very high bandwidth operation. Master-slave ECL shift register bit outputs are directly coupled, without emitter followers, to ECL inputs of output latches that drive the DAC current switches, resulting in substantially reduced power consumption and chip area. Saturation of the emitter-coupled NPN transistors of the latch circuit is avoided by providing an upper supply voltage level for the load resistors of the master-slave shift register bits that is one diode drop lower than the upper supply voltage level for the load resistors of the latch circuit. A unique ECL one-shot circuit responds to an external latch enable control signal having TTL logic levels to produce internal complementary ECL enable signals that enable the output latches.

摘要翻译： 每个具有TTL逻辑电平的串行到并行转换器接收时钟信号和连续串行输入数据串，产生用于驱动数模转换器（DAC）的电流开关的并行输出。 数据和时钟信号各自通过一对发射极耦合的差分横向PNP晶体管转换为ECL逻辑电平，其具有耦合到一对NPN电流镜像电路的集电极，其输出驱动一对NPN的基极和发射极 射极跟随器晶体管，导致非常高的带宽操作。 主从ECL移位寄存器位输出直接耦合到无发射极跟随器，用于驱动DAC电流开关的输出锁存器的ECL输入，从而大大降低功耗和芯片面积。 通过为主从移位寄存器位的负载电阻提供较高的电源电压来避免锁存电路的发射极耦合NPN晶体管的饱和，该电平为比二极管降低负载电阻 锁存电路。 独特的ECL单稳态电路响应具有TTL逻辑电平的外部锁存使能控制信号，以产生使输出锁存器能够实现的内部互补ECL使能信号。

公开(公告)号：US4503548A

公开(公告)日：1985-03-05

申请号：US365824

申请日：1982-04-05

申请人： Jesse C. Phillips

发明人： Jesse C. Phillips

IPC分类号： G04F1/00 ,  H03K21/12 ,  H03K21/14 ,  G06M3/02

CPC分类号： H03K21/12 ,  G04F1/005

摘要： A timer device includes a multiple bit storage circuit to store a numerical value as a series of binary bits and evaluation circuitry to simultaneously compare the value stored in the storage circuitry with a predetermined value. This invention further includes a counter circuit consisting of a multiple bit storage circuit to store an initial counter value, a counter circuit to receive the initial counter value and to decrement the counter in response to a clock signal and an evaluation circuit to produce an output when the counter value is identical to a circuit defined value.

摘要翻译： 定时器装置包括多位存储电路，用于将数值存储为一系列二进制位和评估电路，以将存储电路中存储的值与预定值同时进行比较。 本发明还包括由存储初始计数器值的多位存储电路组成的计数器电路，接收初始计数器值的计数器电路以及响应于时钟信号递减计数器和评估电路以产生输出 计数器值与电路定义值相同。

公开(公告)号：US4282488A

公开(公告)日：1981-08-04

申请号：US76042

申请日：1979-09-17

申请人： Stanley R. C. Norman ,  Kam B. Tin

发明人： Stanley R. C. Norman ,  Kam B. Tin

IPC分类号： H03K5/1252 ,  H03K21/14 ,  H03K5/22

CPC分类号： H03K5/1252 ,  H03K21/14

摘要： A noise eliminator circuit for use in a decoding circuit. A flip-flop is used to delay a first pulse train by the pulse width of a second pulse train so that pulse level transitions of the first pulse train occur non-coincident with the pulse level transitions of a synchronously generated third pulse train.

摘要翻译： 一种用于解码电路的噪声消除器电路。 触发器用于将第一脉冲串延迟第二脉冲序列的脉冲宽度，使得第一脉冲串的脉冲电平转换与同步产生的第三脉冲序列的脉冲电平转换不一致。

公开(公告)号：US20170248704A1

公开(公告)日：2017-08-31

申请号：US15430894

申请日：2017-02-13

申请人： THERMO EBERLINE LLC

发明人： Greg Holger NELSON ,  Phillip Edward BEESON ,  Alan John LAING

IPC分类号： G01T1/15 ,  H03K3/012 ,  H03K21/14

CPC分类号： G01T1/15 ,  G01T1/171 ,  H03K3/012 ,  H03K21/14

摘要： A system includes a pulse counter having a selectable pulse counter read-out rate, a pulse counter read-out (PCRO) storage register that stores a PCRO count, and a pulse-burst counter that has a pulse-burst counter read-out rate that is faster than all but the fastest selectable pulse counter read-out rate, a subtractor module in electronic communication with the pulse counter and the PCRO that subtracts the PCRO count from the pulse counter read-out count to output an uncorrected pulse count, a selection module in electronic communication with the pulse-burst counter that selects the pulse counter read-out rate in response to input from the pulse-burst counter, a multiplexer in electronic communication with the subtractor module and the selection module, the multiplexer selecting from among at least two dead-time correction transforms, the transform corresponding to the selected pulse counter read-out rate, and a control-and-readout module that outputs a dead-time corrected pulse rate.

公开(公告)号：US5497406A

公开(公告)日：1996-03-05

申请号：US314661

申请日：1994-09-29

申请人： Jader A. de Lima ,  Yong-Uk Lee ,  Pierre J. Nunzi

发明人： Jader A. de Lima ,  Yong-Uk Lee ,  Pierre J. Nunzi

IPC分类号： H04N5/06 ,  H03K3/64 ,  H03K3/72 ,  H03K3/78 ,  H03K4/00 ,  H04N3/233 ,  H04N5/44 ,  G06F9/00 ,  H03K21/14

CPC分类号： H03K3/78 ,  H03K3/64 ,  H03K4/00 ,  H04N3/2335

摘要： A periodic signal is produced by counting pulses of a clock during a given period of time. The number of pulses counted is divided by a whole number. A count is then made of a batch of pulses of this clock, the number of pulses in this batch corresponds to the quotient of this division. At each time a batch is completed, a value of a periodic signal is produced.

摘要翻译： 通过在给定时间段内对时钟的脉冲进行计数来产生周期性信号。 计数的脉冲数除以整数。 然后由该时钟的一批脉冲计数，该批次中的脉冲数对应于该分频的商。 在每次完成批次时，产生周期性信号的值。

公开(公告)号：US5337338A

公开(公告)日：1994-08-09

申请号：US11618

申请日：1993-02-01

申请人： Todd Sutton ,  Sherman Gregory ,  Joan T. Waltman ,  Katherine W. White

发明人： Todd Sutton ,  Sherman Gregory ,  Joan T. Waltman ,  Katherine W. White

IPC分类号： H03M5/04 ,  H03M7/00 ,  H03K21/14

CPC分类号： H03M5/04

摘要： A pulse density modulation circuit has a counter which produces a most significant bit through a least significant bit output based on a clock input. The circuit also has a comparator with two sets of most significant bit through least significant bit inputs that produces an output based on a comparison of the two sets of inputs. The first set of comparator most significant bit through least significant bit inputs receives respectively a most significant bit through a least significant bit of an input reference signal. The second set of comparator most significant bit through least significant bit inputs receives the counter most significant bit through least significant bit output in a non-sequential bit order. The non-sequential bit order can be a bit reversed order wherein the counter most significant bit through least significant bit output are respectively connected to the comparator least significant bit through most significant bit input. The circuit may further filter the comparator output to provide a resultant analog output signal.

摘要翻译： 脉冲密度调制电路具有基于时钟输入通过最低有效位输出产生最高有效位的计数器。 该电路还具有比较器，其具有两组最高有效位通过最低有效位输入，其基于两组输入的比较产生输出。 第一组比较器最高有效位通过最低有效位输入通过输入参考信号的最低有效位分别接收最高有效位。 第二组比较器最高有效位通过最低有效位输入以非顺序位顺序通过最低有效位输出接收计数器最高有效位。 非顺序位顺序可以是位反转顺序，其中通过最低有效位输出的计数器最高有效位分别通过最高有效位输入连接到比较器最低有效位。 电路可以进一步对比较器输出进行滤波以提供合成的模拟输出信号。

公开(公告)号：US5309494A

公开(公告)日：1994-05-03

申请号：US967680

申请日：1992-10-26

申请人： Udo Grehl

发明人： Udo Grehl

IPC分类号： G06F7/50 ,  G06F7/505 ,  G06F7/62 ,  G11C19/00 ,  H03K21/14 ,  H03K23/58 ,  H03M13/41 ,  H03K21/02 ,  H03K21/08 ,  H03M13/00

CPC分类号： G06F7/5055 ,  G06F7/62 ,  G11C19/00 ,  H03K21/14 ,  H03K23/58 ,  H03M13/41

摘要： A circuit configuration includes k linking cells each generating one of k output states from two of k input states. Each of the linking cells have two counters. Each of the counters have a serial data input, a serial data output, and a serial counting width input. The counters increase a counter state loaded through the data input and represent the respectively assigned input state by a value input through the counting width input. Comparators are each connected to the data outputs of two of the counters for serially comparing the two counter states with one another. Multiplexers are each connected to the data outputs of two of the counters for outputting one of the two counter states as an output state under the control of the comparator. Each two further multiplexers are connected upstream of the respective counters and are switched through for loading the counter states with the respectively assigned input states and for comparing the counter states at the data outputs with the counter states at the data inputs of the respective counters.

摘要翻译： 电路配置包括k个链路单元，每个链路单元从k个输入状态中的两个产生k个输出状态之一。 每个链接单元都有两个计数器。 每个计数器都有串行数据输入，串行数据输出和串行计数宽度输入。 计数器增加通过数据输入加载的计数器状态，并通过计数宽度输入输入的值表示分配的输入状态。 比较器各自连接到两个计数器的数据输出，用于将两个计数器状态彼此串行比较。 多路复用器各自连接到两个计数器的数据输出，用于在比较器的控制下输出两个计数器状态之一作为输出状态。 每两个进一步的多路复用器连接在相应计数器的上游，并被切换以加载具有分配的输入状态的计数器状态，并用于将数据输出处的计数器状态与各个计数器的数据输入处的计数器状态进行比较。

公开(公告)号：US4535466A

公开(公告)日：1985-08-13

申请号：US521803

申请日：1983-08-10

申请人： Frank A. Palvolgyi

发明人： Frank A. Palvolgyi

IPC分类号： H03K3/84 ,  H03K21/14

CPC分类号： H03K3/84

摘要： The timer generates a selected number of control pulses per hour, at unpredictable (pseudo-random) intervals, for use with a time lapse video tape recorder used for time studies. The hour is divided into equal intervals to provide the number of samples required per hour, and one trigger pulse is generated randomly timed within each interval. A noise generator drives a counter whose outputs are loaded every Nth clock pulse into an N-stage shift register. The contents of the shift register are shifted out serially at the clock frequency.

摘要翻译： 定时器以不可预测（伪随机）间隔每小时产生一个选定数量的控制脉冲，以便与用于时间研究的时间延迟录像机一起使用。 小时分为等间隔，以提供每小时所需的样品数，并且在每个间隔内随机定时生成一个触发脉冲。 噪声发生器驱动一个计数器，其输出每第N个时钟脉冲被加载到N级移位寄存器中。 移位寄存器的内容以时钟频率串行移出。