公开(公告)号：US08927433B2

公开(公告)日：2015-01-06

申请号：US12969469

申请日：2010-12-15

Applicant: Jin-Yeong Kang

Inventor： Jin-Yeong Kang

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/288 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.

Abstract translation: 提供一种用于形成导电通孔以实现集成电路的三维堆叠结构的技术。 根据本发明的实施例的形成导电通孔的方法包括：通过使用还原将银填充在形成在基板的上部和下部的一个或多个中的通孔结构的内部，以及 为了通过导体连接多个堆叠的衬底，银的沉淀; 通过使银流入其中而填充通孔结构中未填充银的部分; 以及在流动过程中产生的氧化银系列的残留材料升华到填充有银的通孔结构的上层。

公开(公告)号：US20110147938A1

公开(公告)日：2011-06-23

申请号：US12969469

申请日：2010-12-15

Applicant: Jin-Yeong KANG

Inventor： Jin-Yeong KANG

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/288 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.

Abstract translation: 提供一种用于形成导电通孔以实现集成电路的三维堆叠结构的技术。 根据本发明的实施例的形成导电通孔的方法包括：通过使用还原将银填充在形成在基板的上部和下部的一个或多个中的通孔结构的内部，以及 为了通过导体连接多个堆叠的衬底，银的沉淀; 通过使银流入其中而填充通孔结构中未填充银的部分; 以及在流动过程中产生的氧化银系列的残留材料升华到填充有银的通孔结构的上层。

公开(公告)号：US20110147787A1

公开(公告)日：2011-06-23

申请号：US12974708

申请日：2010-12-21

Applicant: Lee Mi DO ,  Kun Sik Park ,  Ji Man Park ,  Dong Pyo Kim ,  Jin Yeong Kang ,  Kyu Ha Baek

Inventor： Lee Mi DO ,  Kun Sik Park ,  Ji Man Park ,  Dong Pyo Kim ,  Jin Yeong Kang ,  Kyu Ha Baek

IPC: H01L51/52 ,  H01L51/56

CPC classification number: H01L51/5212 ,  H01L51/5228

Abstract: An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.

Abstract translation: 提供有机发光二极管（OLED）及其制造方法。 在OLED中，图案化的金属电极位于发光层的上部和下部的一个或多个上，以允许从发光层产生的光发射到图案化的金属电极之间的区域。

公开(公告)号：US07943995B2

公开(公告)日：2011-05-17

申请号：US12068161

申请日：2008-02-04

Applicant: Jin Yeong Kang ,  Seung Yun Lee ,  Kyoung Ik Cho

Inventor： Jin Yeong Kang ,  Seung Yun Lee ,  Kyoung Ik Cho

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/66242 ,  H01L21/84 ,  H01L27/1203

Abstract: Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a source and a drain of the CMOS are formed of SiGe and metal, and thus leakage current is prevented and low power consumption is achieved. Also, heat generation in a chip is suppressed, and a wide operation range may be obtained even at a low voltage.

Abstract translation: 提供了在SOI衬底上实现的NMOS器件，PMOS器件和SiGe HBT器件及其制造方法。 在制造Si基高速器件时，SiGe HBT和CMOS安装在单个SOI衬底上。 特别地，CMOS的源极和漏极由SiGe和金属形成，因此防止漏电流并实现低功耗。 此外，芯片中的发热被抑制，即使在低电压下也可以获得宽的工作范围。

公开(公告)号：US20080099806A1

公开(公告)日：2008-05-01

申请号：US11872308

申请日：2007-10-15

Applicant: Jin Yeong KANG ,  Sang Heung LEE ,  Jin Gun KOO

Inventor： Jin Yeong KANG ,  Sang Heung LEE ,  Jin Gun KOO

IPC: H01L27/146 ,  H01L21/00

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14681

Abstract: Provided are image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by use of silicon-germanium bipolar junction transistor complementary metal oxide semiconductor (SiGe BiCMOS) technology. In the image sensor, a PD employs a floating-base-type SiGe HBT unlike a pn-junction-based CMOS image sensor (CIS). A floating base of the SiGe HBT produces a positive (+) voltage with respect to a collector during an exposure process, and the HBT performs a reverse bipolar operation due to the positive voltage so that the collector and an emitter exchange functions. In particular, since the SiGe HBT obtains a current gain ten times as high as that of a typical bipolar device even during the reverse operation, the SiGe HBT cannot only sense an optical (image) current signal but also amplify the optical current signal. Thus, the image sensor requires only three transistors in a pixel so that the degree of integration can increase. Also, the floating base of the HBT is a SiGe or SiGeC epitaxial layer with a very small thickness of 150 Å or less, and even heavily doped B ions are barely thermally diffused due to the properties of the SiGe or SiGeC layer. As a result, the sensitivity of signals can improve in the short wavelength region, thus easily balancing three colors. Furthermore, since the image sensor is a direct signal current amplification type mechanism and senses an optical signal current in a steady mode, a sensing signal has excellent linearity, and thus both a sensing mechanism and control circuit are very simple.

Abstract translation: 提供了具有异质结双极晶体管（HBT）的图像传感器及其制造方法。 图像传感器通过使用硅 - 锗双极结型晶体管互补金属氧化物半导体（SiGe BiCMOS）技术制造。 在图像传感器中，PD采用基于pn结的CMOS图像传感器（CIS）的浮置型SiGe HBT。 SiGe HBT的浮动基极在曝光过程中产生相对于集电极的正（+）电压，并且HBT由于正电压而执行反向双极性操作，使得集电极和发射极交换功能起作用。 特别是，由于SiGe HBT即使在反向工作时也能获得比典型双极型器件高十倍的电流增益，所以SiGe HBT不仅可以检测光学（图像）电流信号，还可以放大光电流信号。 因此，图像传感器仅需要像素中的三个晶体管，使得集成度可以增加。 此外，HBT的浮动基底是具有150或更小厚度的非常小的SiGe或SiGeC外延层，并且由于SiGe或SiGeC层的性质，甚至重掺杂的B离子几乎没有热扩散。 结果，信号的灵敏度可以在短波长区域内改善，从而容易平衡三种颜色。 此外，由于图像传感器是直接信号电流放大型机构，并且在稳定模式下感测光信号电流，所以感测信号具有优异的线性度，因此感测机构和控制电路都非常简单。

公开(公告)号：US07094617B2

公开(公告)日：2006-08-22

申请号：US10912614

申请日：2004-08-04

Applicant: Kyu Hwan Shim ,  Young Joo Song ,  Sang Hoon Kim ,  Jin Yeong Kang

Inventor： Kyu Hwan Shim ,  Young Joo Song ,  Sang Hoon Kim ,  Jin Yeong Kang

IPC: H01L21/00

CPC classification number: H01L29/127 ,  B82Y10/00 ,  B82Y20/00 ,  H01L31/102 ,  H01L33/08 ,  H01L33/18

Abstract: An optoelectronic device and a method of manufacturing the same which the optoelectronic effect such as light emission or light reception can be increased by forming a dual-structural nano dot to enhance the confinement density of electrons and holes are provided. The optoelectronic device comprises an electron injection layer, a nano dot, and a hole injection layer. The nano dot has a dual structure composed of an external nano dot and an internal dot. The method of manufacturing the optoelectronic device comprises the steps of forming an electron injection layer on a semiconductor substrate; growing nano dot layer on the electron injection layer by an epi-growth method; heating the nano dot layer so that the nano dot has a dual structure composed of an external nano dot and an internal nano dot; and forming a hole injection layer on the overall structure.

Abstract translation: 提供了通过形成双结构纳米点以增强电子和空穴的限制密度来提高光发射或光接收等光电效应的光电子器件及其制造方法。 光电子器件包括电子注入层，纳米点和空穴注入层。 纳米点具有由外部纳米点和内部点组成的双重结构。 制造光电器件的方法包括以下步骤：在半导体衬底上形成电子注入层; 通过外延生长法在电子注入层上生长纳米点层; 加热纳米点层，使得纳米点具有由外部纳米点和内部纳米点组成的双重结构; 并在整个结构上形成空穴注入层。

公开(公告)号：US06346861B2

公开(公告)日：2002-02-12

申请号：US09733837

申请日：2000-12-07

Applicant: Young-Ho Kim ,  Sang-Heung Lee ,  Heung-Soo Rhee ,  Jin-Yeong Kang

Inventor： Young-Ho Kim ,  Sang-Heung Lee ,  Heung-Soo Rhee ,  Jin-Yeong Kang

IPC: H03L7089

CPC classification number: H03L7/107 ,  H03D13/004 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/18

Abstract: A phase locked loop (PLL) is use in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.

Abstract translation: 锁相环（PLL）在诸如混频器，载波频率等的无线电通信系统中使用。 锁相环（PLL）包括用于比较参考信号的相位/频率和反馈信号的相位/频率检测器。 相位/频率检测器包括：与非门逻辑电路，用于对第一信号进行NAND和第二信号以输出NAND信号; 第一锁存单元，用于锁存所述NAND信号并响应于参考频率输出所述第一信号; 以及第二锁存单元，用于锁存所述NAND信号并响应于反馈频率输出所述第二信号。 锁相环（PLL）还包括滤波器控制器，用于响应于相位/频率检测器的输出信号来改变低通滤波器的带宽。

公开(公告)号：US08247854B2

公开(公告)日：2012-08-21

申请号：US12899473

申请日：2010-10-06

Applicant: Jin Yeong Kang

Inventor： Jin Yeong Kang

IPC: H01L31/062

CPC classification number: H01L27/14645 ,  H01L27/1461 ,  H01L27/14614 ,  H01L27/14689

Abstract: Disclosed is a CMOS image sensor and a manufacturing method thereof. According to an aspect of the present invention, each pixel of CMOS image sensor includes a photo detector that includes an electon Collection layer doped with a concentration of 5×1015/cm3 to 2×1016/cm3; and a transfer transistor that is connected to the photo detector and is formed of a vertical type trench gate of which the equivalent oxide thickness is 120 Å or more.

Abstract translation: 公开了CMOS图像传感器及其制造方法。 根据本发明的一个方面，CMOS图像传感器的每个像素包括光电检测器，其包括以5×10 15 / cm 3至2×10 16 / cm 3的浓度掺杂的电子收集层; 以及连接到光检测器并由等效氧化物厚度为120以上的垂直型沟槽栅极形成的转移晶体管。

公开(公告)号：US07855366B2

公开(公告)日：2010-12-21

申请号：US12111830

申请日：2008-04-29

Applicant: Kun Sik Park ,  Yong Sun Yoon ,  Bo Woo Kim ,  Jin Yeong Kang ,  Jong Moon Park ,  Seong Wook Yoo

Inventor： Kun Sik Park ,  Yong Sun Yoon ,  Bo Woo Kim ,  Jin Yeong Kang ,  Jong Moon Park ,  Seong Wook Yoo

IPC: G01J5/20

CPC classification number: G01J5/20 ,  H01L21/762 ,  H01L27/1203

Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.

Abstract translation: 提供了一种基于BJT（双极结型晶体管）的非制冷IR传感器及其制造方法。 基于BJT的非制冷红外传感器包括：基板; 至少一个BJT，其形成为与衬底分开浮动; 以及形成在所述至少一个BJT的上表面上的吸热层，其中所述BJT根据通过所述吸热层吸收的热量来改变输出值。 因此，可以提供能够通过CMOS兼容工艺实现的BJT系非冷却IR传感器，并获得更优异的温度变化检测特性。

公开(公告)号：US07741665B2

公开(公告)日：2010-06-22

申请号：US11872922

申请日：2007-10-16

Applicant: Jin Yeong Kang ,  Jin Gun Koo ,  Sang Heung Lee

Inventor： Jin Yeong Kang ,  Jin Gun Koo ,  Sang Heung Lee

IPC: H01L31/062 ,  H01L31/113

CPC classification number: H01L27/14689 ,  H01L27/14609

Abstract: Provided are a high-quality CMOS image sensor and a photo diode, which can be fabricated in sub-90 nm regime using nanoscale CMOS technology. The photo diode includes: a p-type well; an internal n-type region formed under a surface of the p-type well; and a surface p-type region including a highly doped p-type SiGeC epitaxial layer or a polysilicon layer deposited on a top surface of the p-type well over the internal n-type region. The image sensor includes: a photo diode including an internal n-type region and a surface p-type region; a transfer transistor for transmitting photo-charges generated in the photo diode to a floating diffusion node; and a driving transistor for amplifying a variation in an electric potential of the floating diffusion node due to the photo-charges. The image sensor further includes a floating metal layer for functioning as the floating diffusion node and applying an electric potential from a drain of the transfer transistor to a gate of the driving transistor.

Abstract translation: 提供了一种高质量CMOS图像传感器和光电二极管，其可以使用纳米级CMOS技术在亚90nm范围内制造。 光电二极管包括：p型阱; 形成在p型阱的表面下的内部n型区域; 以及表面p型区域，其包括在内部n型区域上沉积在p型阱的顶表面上的高掺杂p型SiGeC外延层或多晶硅层。 图像传感器包括：包含内部n型区域和表面p型区域的光电二极管; 用于将在光电二极管中产生的光电荷传输到浮动扩散节点的传输晶体管; 以及用于放大由于光电荷引起的浮动扩散节点的电位变化的驱动晶体管。 图像传感器还包括浮动金属层，用作浮动扩散节点并将电势从传输晶体管的漏极施加到驱动晶体管的栅极。