公开(公告)号：US06346861B2

公开(公告)日：2002-02-12

申请号：US09733837

申请日：2000-12-07

申请人： Young-Ho Kim ,  Sang-Heung Lee ,  Heung-Soo Rhee ,  Jin-Yeong Kang

发明人： Young-Ho Kim ,  Sang-Heung Lee ,  Heung-Soo Rhee ,  Jin-Yeong Kang

IPC分类号： H03L7089

CPC分类号： H03L7/107 ,  H03D13/004 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/18

摘要： A phase locked loop (PLL) is use in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.

摘要翻译： 锁相环（PLL）在诸如混频器，载波频率等的无线电通信系统中使用。 锁相环（PLL）包括用于比较参考信号的相位/频率和反馈信号的相位/频率检测器。 相位/频率检测器包括：与非门逻辑电路，用于对第一信号进行NAND和第二信号以输出NAND信号; 第一锁存单元，用于锁存所述NAND信号并响应于参考频率输出所述第一信号; 以及第二锁存单元，用于锁存所述NAND信号并响应于反馈频率输出所述第二信号。 锁相环（PLL）还包括滤波器控制器，用于响应于相位/频率检测器的输出信号来改变低通滤波器的带宽。

公开(公告)号：US08927433B2

公开(公告)日：2015-01-06

申请号：US12969469

申请日：2010-12-15

申请人： Jin-Yeong Kang

发明人： Jin-Yeong Kang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/288 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.

摘要翻译： 提供一种用于形成导电通孔以实现集成电路的三维堆叠结构的技术。 根据本发明的实施例的形成导电通孔的方法包括：通过使用还原将银填充在形成在基板的上部和下部的一个或多个中的通孔结构的内部，以及 为了通过导体连接多个堆叠的衬底，银的沉淀; 通过使银流入其中而填充通孔结构中未填充银的部分; 以及在流动过程中产生的氧化银系列的残留材料升华到填充有银的通孔结构的上层。

公开(公告)号：US08513655B2

公开(公告)日：2013-08-20

申请号：US12974708

申请日：2010-12-21

申请人： Lee Mi Do ,  Kun Sik Park ,  Ji Man Park ,  Dong Pyo Kim ,  Jin-Yeong Kang ,  Kyu Ha Baek

发明人： Lee Mi Do ,  Kun Sik Park ,  Ji Man Park ,  Dong Pyo Kim ,  Jin-Yeong Kang ,  Kyu Ha Baek

IPC分类号： H01J19/42

CPC分类号： H01L51/5212 ,  H01L51/5228

摘要： An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes.

摘要翻译： 提供有机发光二极管（OLED）及其制造方法。 在OLED中，图案化的金属电极位于发光层的上部和下部的一个或多个上，以允许从发光层产生的光发射到图案化的金属电极之间的区域。

公开(公告)号：US06980075B2

公开(公告)日：2005-12-27

申请号：US10714287

申请日：2003-11-13

申请人： Bongki Mheen ,  Seok-bong Hyun ,  Dong Woo Suh ,  Jin-Yeong Kang

发明人： Bongki Mheen ,  Seok-bong Hyun ,  Dong Woo Suh ,  Jin-Yeong Kang

IPC分类号： H01F17/00 ,  H01L21/02 ,  H01L27/08 ,  H01F5/00

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L27/08

摘要： A method for arranging unit inductors of an inductor having metal wiring that can make a full use of self-inductance and mutual-inductance which are determined based on the proportion of the area of an unit inductor and the proportion of the overlapping area with another unit inductor, and an inductor adopting the unit inductor arranging method. The unit inductor arranging method, wherein the inductor includes a first unit inductor, a second inductor and a third inductor, and self-inductance magnitudes of the unit inductors are in the order of the self-inductance of the third inductor>the self-inductance of the second inductor>the self-inductance of the first inductor, includes the steps of: a) coupling one end of the second unit inductor is connected to one end of the first unit inductor and one end of the third unit inductor to the other end of the first unit inductor in order to arrange the first unit inductor between the second and third unit inductors of which mutual-inductance has the largest value in mutual-inductances between the unit inductors; b) coupling the second unit inductor to a first external terminal; and c) coupling the third unit inductor to a second external terminal.

摘要翻译： 一种用于布置具有金属布线的电感器的单元电感器的方法，该电感器可以充分利用基于单位电感器的面积的比例和与另一单元的重叠区域的比例确定的自感和互感 电感器和采用单元电感器布置方法的电感器。 单元电感器布置方法，其中电感器包括第一单元电感器，第二电感器和第三电感器，并且单位电感器的自感大小等于第三电感器的自感量>自感 的第二电感器的自感包括以下步骤：a）耦合第二单元电感器的一端连接到第一单元电感器的一端并且将第三单元电感器的一端连接到另一端 从而将第一单元电感器布置在单元电感器之间的互感中互感具有最大值的第二和第三单元电感器之间; b）将第二单元电感器耦合到第一外部端子; 以及c）将所述第三单元电感器耦合到第二外部端子。

公开(公告)号：US06686640B2

公开(公告)日：2004-02-03

申请号：US10044107

申请日：2002-01-11

申请人： Bongki Mheen ,  Dongwoo Suh ,  Jin-Yeong Kang

发明人： Bongki Mheen ,  Dongwoo Suh ,  Jin-Yeong Kang

IPC分类号： H01L2993

CPC分类号： H01L29/66174 ,  H01L29/66242 ,  H01L29/93

摘要： A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

摘要翻译： 变容二极管包括第一导电类型的半导体衬底，形成在半导体衬底的上部的第二导电类型的高浓度集电区，在第一表面上形成第二导电类型的集电极区 浓度埋集电极区域，形成在高浓度埋集体区域的第二表面上的第二导电类型的高浓度集电极接触区域，形成在集电体上的第一导电类型的高浓度硅 - 锗基区域 形成在硅 - 锗基区上的金属硅化物层，形成为与金属硅化物层接触的第一电极层和形成为与集电极接触区电连接的第二电极层。

公开(公告)号：US08730728B2

公开(公告)日：2014-05-20

申请号：US13614282

申请日：2012-09-13

申请人： Jin-Yeong Kang

发明人： Jin-Yeong Kang

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C11/56

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/045

摘要： An EEPROM cell including a transfer gate that can suppress a data disturbance phenomenon of the EEPROM cell is provided. The EEPROM cell includes: an inverter; a control plate; a tunneling plate; a data output metal oxide semiconductor field effect transistor (MOSFET) that is connected to the inverter; a floating plate that is connected to the inverter; a tunneling capacitor area that is formed between the floating plate and the tunneling plate; and a transfer gate that is connected to the tunneling plate. As the transfer gate is added between a bit line and the tunneling plate of the EEPROM cell, in a standby (or unselected) operation of the EEPROM cell, the tunneling plate is floated.

摘要翻译： 提供了包括可以抑制EEPROM单元的数据干扰现象的传输门的EEPROM单元。 EEPROM单元包括：逆变器; 控制板; 隧道板; 连接到逆变器的数据输出金属氧化物半导体场效应晶体管（MOSFET）; 与变频器连接的浮板; 在浮板和隧道板之间形成的隧道电容器区域; 以及连接到隧道板的传输门。 当传输门被添加在EEPROM单元的位线和隧道板之间时，在EEPROM单元的备用（或未选择）操作中，隧道板浮起来。

公开(公告)号：US08421144B2

公开(公告)日：2013-04-16

申请号：US12796840

申请日：2010-06-09

申请人： Jin-Yeong Kang

发明人： Jin-Yeong Kang

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/7885

摘要： An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer forming a floating gate. The first polysilicon layer is horizontally disposed in series with the second polysilicon layer and is connected to the third polysilicon layer, so that the control gate encloses all of the floating gate except for a tunnel surface of the floating gate.

摘要翻译： 电可擦除可编程只读存储器包括第一多晶硅层，第二多晶硅层和第三多晶硅层，第一多晶硅层和第三多晶硅层形成控制栅极，第二多晶硅层形成浮栅。 第一多晶硅层与第二多晶硅层串联水平设置并连接到第三多晶硅层，使得除了浮动栅极的隧道表面之外，控制栅极包围所有浮置栅极。

公开(公告)号：US20050139862A1

公开(公告)日：2005-06-30

申请号：US10677665

申请日：2003-10-01

申请人： Chan Park ,  Seung-Yun Lee ,  Shanghoon Kim ,  Jin-Yeong Kang

发明人： Chan Park ,  Seung-Yun Lee ,  Shanghoon Kim ,  Jin-Yeong Kang

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/072

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

摘要： Provided are a self-aligned heterojunction bipolar transistor that can prevent electrical short-circuit caused by the agglomeration during the formation of a silicide electrode, minimize resistance by forming thick base electrodes, minimize the parasitic resistance of the base and parasitic capacitance between the base and the collector, and thus improve the process stability and economical efficiency by ruling out a wet-etching process and performing a selective thin film growing process once, and a manufacturing method thereof. The heterojunction bipolar transistor of this research includes: a collector and a collector electrode formed within a silicon substrate; base electrodes formed on the collector and including a protrusion having a first opening and a body having a second opening for exposing the surface of the collector; a base epitaxial layer grown selectively on the collector exposed thorough the first opening; sidewall spacers formed on the sidewalls of the second opening; an emitter electrode formed on the base epitaxial layer in the shape of an overhang that covers the sidewall spacers; and an insulation layer inserted between the overhang of the emitter electrode and the base electrodes and connected to the sidewall spacers.

摘要翻译： 提供了一种自对准异质结双极晶体管，其可以防止在形成硅化物电极期间由聚集引起的电短路，通过形成厚的基极电极使电阻最小化，使基极的寄生电阻最小化，并且基极和 并且因此通过排除湿式蚀刻工艺和执行选择性薄膜生长工艺一次来提高工艺稳定性和经济性及其制造方法。 该研究的异质结双极晶体管包括：在硅衬底内形成的集电极和集电极; 基底电极形成在集电体上并且包括具有第一开口的突起和具有用于暴露集电体的表面的第二开口的主体; 在通过第一开口暴露的收集器上选择性地生长的基极外延层; 形成在第二开口的侧壁上的侧壁间隔物; 形成在所述基底外延层上的覆盖所述侧壁间隔物的突出形状的发射电极; 以及绝缘层，其插入在发射电极的伸出部和基极之间并与侧壁间隔件连接。

公开(公告)号：US06469609B2

公开(公告)日：2002-10-22

申请号：US09733839

申请日：2000-12-07

申请人： Seung-Yun Lee ,  Jin-Yeong Kang

发明人： Seung-Yun Lee ,  Jin-Yeong Kang

IPC分类号： H01F500

CPC分类号： H01F41/041 ,  H01F5/003 ,  Y10T29/4902 ,  Y10T29/49071

摘要： The present invention relates to a method of fabricating an inductor capable of improving a quality factor and decreasing a series resistance by using as a material of the inductor silver smaller in a specific resistance than aluminum used conventionally. The method of fabricating an inductor according to the present invention includes the following steps. A first step is of forming a first metal layer on a first insulating layer, patterning said first metal layer, and forming a second insulating layer on the resultant structure. A second step is of patterning said second insulating layer to form a via hole and forming a plug in said via hole. A third step is of forming a third insulating layer on the resultant structure and patterning said third insulating layer to form a spiral groove. A fourth step is of forming a second metal layer in said spiral groove to form an inductor. And a fifth step is of forming a fourth insulating layer for protecting said inductor from a mechanical force or materials causing a chemical reaction.

摘要翻译： 本发明涉及一种制造电感器的方法，该电感器通过使用电感器银的材料，其电阻比常规使用的铝的电阻率小，可以提高品质因数并降低串联电阻。 根据本发明的制造电感器的方法包括以下步骤。 第一步骤是在第一绝缘层上形成第一金属层，图案化所述第一金属层，并在所得结构上形成第二绝缘层。 第二步是图案化所述第二绝缘层以形成通孔并在所述通孔中形成插头。 第三步骤是在所得结构上形成第三绝缘层，并且图案化所述第三绝缘层以形成螺旋槽。 第四步骤是在所述螺旋槽中形成第二金属层以形成电感器。 并且第五步是形成用于保护所述电感器免受机械力或导致化学反应的材料的第四绝缘层。

公开(公告)号：US5389796A

公开(公告)日：1995-02-14

申请号：US171408

申请日：1993-12-22

申请人： Sung-Weon Kang ,  Jin-Yeong Kang

发明人： Sung-Weon Kang ,  Jin-Yeong Kang

IPC分类号： H01J21/06 ,  H01J1/34 ,  H01J9/12 ,  H01J17/06 ,  H01J19/24 ,  H01J21/04 ,  H01J40/16 ,  H01L21/331 ,  H01L31/12 ,  H01L29/06

CPC分类号： H01J1/34 ,  H01J17/066 ,  H01J21/04

摘要： A vacuum transistor having an optical gate in which an optical signal is radiated from the optical gate. The transistor has a silicon substrate; an insulating layer deposited on said silicon substrate, the insulating layer having a recess portion formed by an etching method; an optical source for radiating the optical signal and serving as said optical gate; and two electrodes formed on said insulating layer and separated from each other under a vacuum or an atmosphere. One of the electrodes receives the optical signal and is an electron emitting electrode for emitting electrons, and the other electrode is an electron collecting electrode for collecting the electrons emitted from said electron emitting electrode. The electron emitting electrode is formed beneath said optical source under a vacuum or an atmosphere and is connected to ground; and said electron collecting electrode is connected to a power source. The amount of current flowing in said electron collecting electrode may be adjusted by the intensity of the optical signal from said optical source. The mobility of electrons between the electron emitting electrode and the electron collecting electrode is further improved owing to a vacuum state or an atmosphere state of the electron transferring path.

摘要翻译： 一种具有光栅的真空晶体管，其中光信号从光栅辐射。 晶体管具有硅衬底; 沉积在所述硅衬底上的绝缘层，所述绝缘层具有通过蚀刻方法形成的凹部; 用于辐射光信号并用作所述光栅的光源; 以及形成在所述绝缘层上并在真空或大气中彼此分离的两个电极。 一个电极接收光信号，并且是用于发射电子的电子发射电极，另一个电极是用于收集从所述电子发射电极发射的电子的电子收集电极。 电子发射电极在真空或大气下在所述光源下面形成并连接到地面; 并且所述电子收集电极连接到电源。 可以通过来自所述光源的光信号的强度来调节在所述电子收集电极中流动的电流量。 由于电子传输路径的真空状态或气氛状态，电子发射电极和电子收集电极之间的电子迁移率进一步提高。