公开(公告)号：US12061853B2

公开(公告)日：2024-08-13

申请号：US17497400

申请日：2021-10-08

申请人： Arm Limited

发明人： Rainer Herberholz ,  Supreet Jeloka

IPC分类号： G06F30/3312 ,  G06F111/04 ,  G06F119/12

CPC分类号： G06F30/3312 ,  G06F2111/04 ,  G06F2119/12

摘要： Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.

公开(公告)号：US12041713B2

公开(公告)日：2024-07-16

申请号：US15683901

申请日：2017-08-23

申请人： Teradyne, Inc.

发明人： Jan Paul Antonie van der Wagt ,  Bradley A. Phillips

IPC分类号： H05K1/02 ,  G06F1/10 ,  G06F30/30 ,  G06F30/3312 ,  G06F119/12 ,  H03K19/003

CPC分类号： H05K1/0248 ,  G06F1/10 ,  G06F30/30 ,  G06F30/3312 ,  H03K19/00323 ,  H05K1/0298 ,  G06F2119/12

摘要： An example method performed for a circuit path includes: receiving signals in the circuit path; and controlling states of the signals in the circuit path based on skews produced by circuits electrically connected in series in the circuit path. The states are controlled by inverting or not inverting the signals in the circuit path so that skews produced by different circuits in the circuit paths at least partially cancel.

公开(公告)号：US11966678B2

公开(公告)日：2024-04-23

申请号：US17540774

申请日：2021-12-02

申请人： Synopsys, Inc.

发明人： Ruijing Shen ,  Li Ding

IPC分类号： G06F30/3312 ,  G06F30/31 ,  G06F30/3315 ,  G06F119/12

CPC分类号： G06F30/3312 ,  G06F30/31 ,  G06F30/3315 ,  G06F2119/12

摘要： A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

公开(公告)号：US20240086612A1

公开(公告)日：2024-03-14

申请号：US18517400

申请日：2023-11-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Hsiang HUANG ,  Fong-Yuan CHANG ,  Clement Hsingjen WANN ,  Chih-Hsin KO ,  Sheng-Hsiung CHEN ,  Li-Chun TIEN ,  Chia-Ming HSU

IPC分类号： G06F30/392 ,  G06F30/3312 ,  G06F30/367 ,  G06F30/398 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC分类号： G06F30/392 ,  G06F30/3312 ,  G06F30/367 ,  G06F30/398 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785 ,  G06F2111/20

摘要： An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

公开(公告)号：US20240020451A1

公开(公告)日：2024-01-18

申请号：US18361467

申请日：2023-07-28

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Sheng-Hsiung Chen ,  Chun-Chen Chen ,  Shao-huan Wang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Ren-Zheng Liao ,  Meng-Xiang Lee

IPC分类号： G06F30/392 ,  G06F30/327 ,  G06F30/3312 ,  G06F30/367 ,  G06F30/398

CPC分类号： G06F30/392 ,  G06F30/327 ,  G06F30/3312 ,  G06F30/367 ,  G06F30/398 ,  G06F2111/04

摘要： An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.

公开(公告)号：US11868694B1

公开(公告)日：2024-01-09

申请号：US16874197

申请日：2020-05-14

申请人： Synopsys, Inc.

发明人： Bojan Mihajlovic ,  Alexander Rabinovitch ,  Fei Chen

IPC分类号： G06F30/3312 ,  G06F119/12

CPC分类号： G06F30/3312 ,  G06F2119/12

摘要： A system is disclosed that includes a memory, and a processor configured to perform operations stored in the memory. The processor performs the operations to analyze each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements. The processor further performs the operations to discard one or more cycles of the clock signal pattern of the clock from emulation that do not include the edge of the clock signal pattern that causes at least one sequential element of the first set of sequential elements to change the output and emulate remaining cycles of the clock signal pattern of the clock.

公开(公告)号：US11836433B2

公开(公告)日：2023-12-05

申请号：US17592404

申请日：2022-02-03

申请人： Synopsys, Inc.

发明人： John Edward Barth ,  Jeffrey C. Herbert ,  Matthew Christopher Lanahan

IPC分类号： G06F30/39 ,  G06F30/3312 ,  G06F30/3315

CPC分类号： G06F30/39 ,  G06F30/3312 ,  G06F30/3315

摘要： A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

公开(公告)号：US11829695B2

公开(公告)日：2023-11-28

申请号：US17402632

申请日：2021-08-16

申请人： S2C Limited

发明人： Jifeng Zhang ,  Chuan Li

IPC分类号： G06F30/34 ,  G06F30/392 ,  G06F30/3312 ,  G06F30/327

CPC分类号： G06F30/34 ,  G06F30/327 ,  G06F30/3312 ,  G06F30/392

摘要： A method for logic design partitioning includes: collecting an RTL design file used for describing a logic circuit; performing syntax analysis processing on the RTL design file; extracting an always object and an assign object from logic model objects, and encapsulating the always object and the assign object, respectively; constructing and generating a hypergraph-based data structure; performing attribute analysis, and obtaining operating frequency information by processing according to clock domain information; associating and storing the clock domain information and the operating frequency information with corresponding nodes; and performing partitioning processing to obtain corresponding partitioned data. By means of the solutions of the present invention, other processing at the back end of the flow is not affected, the partitioning time is reduced and the partitioning efficiency is improved. Meanwhile, the logic content in chip design is partitioned efficiently, reasonably and correctly.

公开(公告)号：US11783106B2

公开(公告)日：2023-10-10

申请号：US17227748

申请日：2021-04-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ravi Babu Pittu ,  Chung-Hsing Wang ,  Sung-Yen Yeh ,  Li Chung Hsu

IPC分类号： G06F9/455 ,  G06F30/3312 ,  G06F30/39 ,  G06F30/367 ,  G06F119/12

CPC分类号： G06F30/3312 ,  G06F30/367 ,  G06F30/39 ,  G06F2119/12

摘要： A method and system for manufacturing a circuit is disclosed. In some embodiments, the system includes: at least one processor configured to: generate a first timing library for a first set of circuit elements for a first set of input parameters based on device characteristics for each of the circuit elements in the first set of circuit elements, and storing the determined device characteristics in a database; and generating a second timing library for a second set of circuit elements for a second set of input parameters based on device characteristics previously stored in the database for a first subset of the second set of circuit elements and determining device characteristics for a second subset of the second set of circuit elements using one of an aging simulation or a stress simulation; and a circuit generation system, coupled to the at least one processor, the circuit generation system configured to form a circuit on a substrate, wherein the circuit includes at least one of the first set of circuit elements or the second set of circuit elements.

公开(公告)号：US11775717B2

公开(公告)日：2023-10-03

申请号：US17254242

申请日：2019-12-30

申请人： CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.

发明人： Yuqian Cedric Wong ,  Shuiyin Yao ,  Hongchang Liang ,  Zhimin Tang

IPC分类号： G06F30/3312 ,  G06F30/327 ,  G06F119/06 ,  G06F119/12

CPC分类号： G06F30/3312 ,  G06F30/327 ,  G06F2119/06 ,  G06F2119/12

摘要： A chip design method, a chip design device, a chip, and an electronic device are provided. The chip design method includes: determining at least one power state of the chip, one power state of the at least one power state including switch states of respective power domains on the chip in a chip operation mode, and the at least one power state including a first power state; determining control signals sent by changed power domains in the respective power domains in a case where a power state of the chip is switched to the first power state, in a case where the power state of the chip is switched to the first power state, switch states of the changed power domains changing; and analyzing timing dependency between the control signals to determine timing dependency between power domains to which the control signals act in the first power state.