公开(公告)号：US20240338174A1

公开(公告)日：2024-10-10

申请号：US18748393

申请日：2024-06-20

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Guangning Fu ,  Tengyi Lin

IPC分类号： G06F5/16 ,  G06F9/38 ,  G06F17/16

CPC分类号： G06F5/16 ,  G06F9/3836 ,  G06F17/16

摘要： This application provides a matrix computing method, a chip, and a related device. The chip includes a first buffer, is configured to buffer a first vector, and a second buffer is configured to buffer a second vector. A scheduling module generates a selection signal based on a bitmap of the first vector. The selection signal may cause the processing element to obtain, from the first buffer, a group of non-zero elements in the first vector, and cause the processing element to obtain, from the second buffer, a group of elements in the second vector. An operation is performed between the first vector and the second vector based on the group of non-zero elements in the first vector and the group of elements in the second vector. In this application, an element whose value is 0 in one vector may be excluded from computing, to reduce a computing amount.

公开(公告)号：US11875244B2

公开(公告)日：2024-01-16

申请号：US18009341

申请日：2022-08-05

申请人： SHANGHAITECH UNIVERSITY

发明人： Hongtu Zhang ,  Yuhao Shu ,  Yajun Ha

IPC分类号： G06N3/0464 ,  G06F5/16

CPC分类号： G06N3/0464 ,  G06F5/16

摘要： An enhanced dynamic random access memory (eDRAM)-based computing-in-memory (CIM) convolutional neural network (CNN) accelerator comprises four P2ARAM blocks, where each of the P2ARAM blocks includes a 5T1C ping-pong eDRAM bit cell array composed of 64×16 5T1C ping-pong eDRAM bit cells. In each of the P2ARAM blocks, 64×2 digital time converters convert a 4-bit activation value into different pulse widths from a row direction and input the pulse widths into the 5T1C ping-pong eDRAM bit cell array for calculation. A total of 16×2 convolution results are output in a column direction of the 5T1C ping-pong eDRAM bit cell array. The CNN accelerator uses the 5T1C ping-pong eDRAM bit cells to perform multi-bit storage and convolution in parallel. An S2M-ADC scheme is proposed to allot an area of an input sampling capacitor of an ABL to sign-numerical SAR ADC units of a C-DAC array without adding area overhead.

公开(公告)号：US11816060B2

公开(公告)日：2023-11-14

申请号：US17465379

申请日：2021-09-02

申请人： Nuvoton Technology Corporation

发明人： Chih-Chiang Chang

IPC分类号： G06F13/42 ,  G06F5/16 ,  G06F13/38

CPC分类号： G06F13/4291 ,  G06F5/16 ,  G06F13/385 ,  G06F13/4286

摘要： An UART interface circuit is provided in the invention. The UART interface circuit is configured in an electronic device. The UART interface circuit includes a baud-rate generating circuit, a control circuit, and a receiving circuit. The baud-rate generating circuit is configured to generate a baud rate and a start-bit cycle. The control circuit obtains the wakeup stable time from the wakeup time circuit of the electronic device and obtains the start-bit cycle from the baud-rate generating circuit. The receiving circuit is configured to capture data from the start bit or the first data bit of UART data. When the electronic device is woken up by the UART data, the control circuit compares the start-bit cycle with the wakeup stable time to direct the receiving circuit to start capturing data from the start bit or the first data bit of the UART data.

公开(公告)号：US20230244443A1

公开(公告)日：2023-08-03

申请号：US18060806

申请日：2022-12-01

申请人： Samsung Electronics Co., Ltd.

发明人： Yewon LEE

IPC分类号： G06F5/16

CPC分类号： G06F5/16

摘要： Disclosed is a MIMO FIFO buffer circuit that reads out data flits at once as many as an internal pointer increment value. The MIMO FIFO buffer circuit includes a MIMO FIFO storage array including ‘Y’ storage blocks, and an internal pointer generator that generates an internal pointer based on an internal pointer increment value indicating the number of data flits to read out at once from among ‘K×X’ data flits stored in K storage blocks out of the ‘Y’ storage blocks. Each of the ‘Y’ and the ‘K’ is a natural number, and the ‘K’ is equal to or less than the ‘Y’, and each of the ‘K’ storage blocks stores ‘X’ data flits.

公开(公告)号：US10949365B2

公开(公告)日：2021-03-16

申请号：US16330677

申请日：2017-09-05

申请人： IoT.nxt BV

发明人： Gysbert Johannes Jacobs ,  Rudi Deodat Du Toit

IPC分类号： G06F13/20 ,  G06F1/08 ,  G06F15/78 ,  G06F5/16 ,  G06F15/00 ,  G06F1/04 ,  H04L29/08 ,  G06F21/76 ,  G06F21/85 ,  H04L29/06 ,  G06F13/42

摘要： The invention relates to a software defined device interface system 10, a software defined device interface, gateway and a method of defining an interface for a device which uses a specific communication protocol for communication purposes. The system 10 includes a microprocessor/processing unit 12.1, 12.2 with a plurality of communication pins and software/firmware. The software/firmware is configured, based on a specific communication protocol which is used by a particular device 30.1-30.4 for communication purposes, to, in runtime, assign/select one or more of the communication pins to form a virtual port to which the particular device 30.1-30.4 can be connected, upon receiving a configuration instruction from a user to implement the specific communication protocol. The software/firmware is further configured to implement the specific communication protocol through the virtual port, to thereby allow for communication between the microprocessor/processing unit 12.1, 12.2 and the device 30.1-30.4, when the device 30.1-30.4 is connected to the pin(s) of the virtual port.

公开(公告)号：US10148586B2

公开(公告)日：2018-12-04

申请号：US15582144

申请日：2017-04-28

申请人： Cisco Technology, Inc.

发明人： Sha Ma ,  Philip Chen

IPC分类号： H04L12/865 ,  H04L12/875 ,  G06F9/48 ,  H04L12/863 ,  H04L12/741 ,  G06F5/16

摘要： A work conserving scheduler can be implemented based on a ranking system to provide the scalability of time stamps while avoiding the fast search associated with a traditional time stamp implementation. Each queue can be assigned a time stamp that is initially set to zero. The time stamp for a queue can be incremented each time a data packet from the queue is processed. To provide varying weights to the different queues, the time stamp for the queues can be incremented at varying rates. The data packets can be processed from the queues based on the tier rank order of the queues as determined from the time stamp associated with each queue. To increase the speed at which the ranking is determined, the ranking can be calculate from a subset of the bits defining the time stamp rather than the entire bit set.

公开(公告)号：US09426016B2

公开(公告)日：2016-08-23

申请号：US14704694

申请日：2015-05-05

申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

发明人： Sheau Jiung Lee ,  Mau-Chung Frank Chang ,  Yanghyo Kim

IPC分类号： H04M11/06 ,  H04L27/38 ,  G06F13/40 ,  G06F5/16 ,  H04L27/36

CPC分类号： H04L27/38 ,  G06F5/16 ,  G06F13/4059 ,  G06F13/4072 ,  G06F13/4278 ,  H04L27/364

摘要： A serializer and de-serializer circuit having self tracking circuitry which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency modulation mechanism (e.g., QAM) for converting digital data bits into a serial analog stream at multiple frequencies for communication over a chip I/O connection. The track pulse generated on the transmitter side is serialized through the same path as the data, and demodulated through the same path in the de-serializer to provide synchronization with the data, without the need for complicated base band processing.

摘要翻译： 具有自我跟踪电路的串行器和解串器电路，其特别适用于将数字数据从一个集成电路（芯片）传送到另一个集成电路（芯片）到另一个用于实现芯片到芯片通信。 这些电路是可扩展的并且利用多频调制机制（例如，QAM），用于将数字数据位转换成多个频率的串行模拟流，用于通过芯片I / O连接进行通信。 在发射机侧产生的跟踪脉冲通过与数据相同的路径进行串行化，并通过解串器中相同的路径解调，以提供与数据的同步，而不需要复杂的基带处理。

公开(公告)号：US09405511B2

公开(公告)日：2016-08-02

申请号：US14524774

申请日：2014-10-27

申请人： STMICROELECTRONICS (CANADA), INC. ,  STMICROELECTRONICS S.r.l.

发明人： John Hogeboom ,  Hock Khor ,  Matteo Alessio Traldi ,  Anton Pelteshki

IPC分类号： H03H7/06 ,  G06F7/72 ,  H03H17/06 ,  G06F5/16 ,  H04L25/02

CPC分类号： G06F7/724 ,  G06F5/16 ,  H03H17/06 ,  H04L25/0272 ,  H04L25/0288

摘要： A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.

摘要翻译： FIR发送架构使用多个驱动器分区，以允许具有不同延迟的信号被驱动器自身求和到输出信号中。 该架构包括第一多路复用器，多个延迟单元，多个符号块，开关块，第二多路复用器和多个驱动器。

公开(公告)号：US20150081934A1

公开(公告)日：2015-03-19

申请号：US14028489

申请日：2013-09-16

申请人： Vinay Gupta ,  Nir Baruch ,  Amit Gur

发明人： Vinay Gupta ,  Nir Baruch ,  Amit Gur

IPC分类号： G06F5/16

CPC分类号： G06F13/1626 ,  G06F1/12 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1689

摘要： A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.

摘要翻译： 用于同步和重新排序在与第一和第二设备接口相关联的第一和第二时钟域之间传输的数据的系统分别包括分离器，仲裁器，事务管理器和读取数据缓冲器。 分离器从第一设备接口的一个或多个数据输入端口接收父读请求，并将其分解成一个或多个读请求。 仲裁器接收一个或多个读取请求，并选择一个读取请求并将其发送到事务管理器。 事务管理器将一个条目分配给读取请求，然后读取请求被发送到读取数据缓冲区。 此后，读取的数据缓冲器将读取的请求发送到第二设备接口，并将接收到的响应数据发送到第一设备接口。

公开(公告)号：US20150052268A1

公开(公告)日：2015-02-19

申请号：US14457367

申请日：2014-08-12

申请人： Sony Computer Entertainment Europe Limited

发明人： Neil Jonathan Brown ,  Phillip Rogers

IPC分类号： G06F5/16 ,  G06F3/06 ,  G06F13/32

CPC分类号： G06F5/16 ,  G06F1/1643 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/4418 ,  G06F9/461 ,  G06F9/4881 ,  G06F11/1438 ,  G06F11/1446 ,  G06F13/32 ,  G06F2003/0691 ,  G09G5/39

摘要： A data processing apparatus comprises a processor having an internal state dependent upon execution of application program code, the processor being configured to generate display data relating to images to be displayed and to buffer display data relating to a most recent period of execution of a currently executing application. The apparatus includes RAM for storing temporary data relating to a current operational state of program execution. The apparatus also includes a data transfer controller configured to transfer data from the RAM relating to the currently executing application, data relating to a current internal state of the processor and buffered display data to suspend data memory, and to transfer data from the suspend data memory to RAM and to the processor to recreate an execution state of an application at a time the suspend instruction was executed, and to retrieve display data relating to the resumed application.

摘要翻译： 数据处理装置包括具有取决于执行应用程序代码的内部状态的处理器，所述处理器被配置为生成与要显示的图像相关的显示数据，并且缓冲与当前执行的最近执行周期有关的显示数据 应用。 该装置包括用于存储与程序执行的当前操作状态有关的临时数据的RAM。 该装置还包括：数据传送控制器，被配置为从与RAM相关的当前执行的应用程序传输数据，与处理器的当前内部状态有关的数据和缓冲的显示数据以暂停数据存储器，并且从挂起数据存储器传送数据 到RAM和处理器，以在执行暂停指令时重新创建应用的执行状态，并且检索与恢复的应用有关的显示数据。