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    PERPENDICULAR STTM FREE LAYER INCLUDING PROTECTIVE CAP
    26.
    发明申请
    PERPENDICULAR STTM FREE LAYER INCLUDING PROTECTIVE CAP 审中-公开
    PERPENDICULAR STTM自由层，包括保护盖

    公开(公告)号：WO2018063255A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/054517

    申请日：2016-09-29

    Applicant: INTEL CORPORATION

    Inventor： OGUZ, Kaan ,  O'BRIEN, Kevin ,  DOYLE, Brian ,  KUO, Charles ,  DOCZY, Mark

    IPC: H01L43/02 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12

    CPC classification number: H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: A perpendicular spin transfer torque memory (pSTTM) device incorporates a magnetic tunnel junction (MTJ) device having a free magnetic stack and a fixed magnetic stack separated by a dielectric tunneling layer. The free magnetic stack includes an uppermost magnetic layer that is at least partially covered by a cap layer. The cap layer is at least partially covered by a protective layer containing at least one of: ruthenium (Ru); cobalt/iron/boron (CoFeB); molybdenum (Mo); cobalt (Co); tungsten (W); or platinum (Pt). The protective layer is at least partially covered by a cap metal layer which may form a portion of MTJ electrode. The protective layer minimizes the occurrence of physical and/or chemical attack of the cap layer by the materials used in the cap metal layer, beneficially improving the interface anisotropy of the MTJ free magnetic layer.

    Abstract translation: 垂直自旋转移力矩存储器（pSTTM）装置结合了具有由电介质隧穿层分开的自由磁性堆叠和固定磁性堆叠的磁性隧道结（MTJ）装置。 自由磁性叠层包括至少部分被覆盖层覆盖的最上面的磁性层。 所述盖层至少部分地被含有以下至少一种的保护层覆盖：钌（Ru）; 钴/铁/硼（CoFeB）; 钼（Mo）; 钴（Co）; 钨（W）; 或铂（Pt）。 保护层至少部分地被可形成MTJ电极的一部分的帽金属层覆盖。 保护层使盖层金属层中使用的材料对盖层的物理和/或化学侵蚀的发生最小化，有利地改善了MTJ自由磁层的界面各向异性。

    THERMAL RESISTOR IN PMTJ STACK DESIGN
    27.
    发明申请
    THERMAL RESISTOR IN PMTJ STACK DESIGN 审中-公开
    PMTJ堆叠设计中的热电阻

    公开(公告)号：WO2018004608A1

    公开(公告)日：2018-01-04

    申请号：PCT/US2016/040454

    申请日：2016-06-30

    Applicant: INTEL CORPORATION

    Inventor： KUO, Charles, C. ,  OGUZ, Kaan ,  DOCZY, Mark, L. ,  DOYLE, Brian, S. ,  O'BRIEN, Kevin, P.

    IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: Disclosed are magnetic tunnel junction (MTJ) devices, computing devices, and related methods. An MTJ device includes an MTJ body, an electrode, and a thermal resistor. The thermal resistor is operably coupled between the MTJ body and the electrode. The thermal resistor includes at least one conductive region including an electrically conductive material. A computing device includes a memory device including at least one MTJ device, which in turn includes at least one thermal resistor between an MTJ body and at least one of a pair of electrodes. A method of forming an MTJ device includes forming an MTJ body, forming at least one electrode, and forming at least one electrically conductive thermal resistor between the MTJ body and the at least one electrode.

    Abstract translation: 公开了磁性隧道结（MTJ）装置，计算装置和相关方法。 MTJ器件包括MTJ主体，电极和热敏电阻。 热电阻器可操作地耦合在MTJ主体和电极之间。 该热敏电阻器包括至少一个包含导电材料的导电区域。 一种计算装置包括存储器装置，该存储器装置包括至少一个MTJ装置，该MTJ装置又包括在MTJ主体与一对电极中的至少一个电极之间的至少一个热电阻器。 形成MTJ器件的方法包括形成MTJ主体，形成至少一个电极，以及在MTJ主体和至少一个电极之间形成至少一个导电热阻。

    INTERCONNECT CAPPING PROCESS FOR INTEGRATION OF MRAM DEVICES AND THE RESULTING STRUCTURES
    28.
    发明申请
    INTERCONNECT CAPPING PROCESS FOR INTEGRATION OF MRAM DEVICES AND THE RESULTING STRUCTURES 审中-公开
    MRAM器件集成与互连结构的互连CAPPING过程

    公开(公告)号：WO2017171716A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2016/024555

    申请日：2016-03-28

    Applicant: INTEL CORPORATION

    Inventor： WIEGAND, Christopher J. ,  GOLONZKA, Oleg ,  RAHMAN, MD Tofizur ,  DOYLE, Brian S. ,  DOCZY, Mark L. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  GHANI, Tahir ,  SURI, Satyarth

    IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

    Abstract translation: 描述了用于集成磁性随机存取存储器（MRAM）器件的互连包覆工艺以及所得到的结构的方法。 在一个示例中，存储器结构包括设置在衬底上方的介电层的沟槽中的互连件，互连件包括设置在沟槽的底部并沿着沟槽的侧壁到介电层的最上表面的扩散阻挡层， 设置在扩散阻挡层上并且凹陷在介电层的最上表面和扩散阻挡层的最上表面下方的导电填充层以及布置在导电填充层上和扩散阻挡层的侧壁部分之间的导电盖层。 存储元件设置在互连的导电盖层上。

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