公开(公告)号：WO2009153624A1

公开(公告)日：2009-12-23

申请号：PCT/IB2008/052448

申请日：2008-06-20

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ROHLEDER, Michael ,  HAY, Gary ,  MUELLER, Stephan ,  THANNER, Manfred

Inventor： ROHLEDER, Michael ,  HAY, Gary ,  MUELLER, Stephan ,  THANNER, Manfred

IPC: G11C29/00 ,  G06F11/16

CPC classification number: G06F11/1666 ,  G06F11/1629 ,  G06F11/167 ,  G06F2201/845 ,  G11C7/1075 ,  G11C29/74 ,  G11C2029/0411

Abstract: A system for distributing available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage.

Abstract translation: 一种用于分发可用存储器资源的系统，包括至少两个随机存取存储器（RAM）元件和RAM路由逻辑。 RAM路由逻辑包括用于动态地将可用存储器资源分配到提供冗余存储器存储器的第一存储器区域和提供非冗余存储器存储器的第二存储器区域的配置逻辑。

公开(公告)号：WO2009142645A1

公开(公告)日：2009-11-26

申请号：PCT/US2008/064679

申请日：2008-05-23

Applicant: AGERE SYSTEMS INC. ,  HARRIS, Edward, B. ,  HOGG, Richard ,  KOHLER, Ross, A. ,  MCPARTLAND, Richard, J. ,  WERNER, Wayne, E.

Inventor： HARRIS, Edward, B. ,  HOGG, Richard ,  KOHLER, Ross, A. ,  MCPARTLAND, Richard, J. ,  WERNER, Wayne, E.

IPC: G06F7/58 ,  G11C5/00

CPC classification number: G06F7/588 ,  G06F11/1008 ,  G11C11/412 ,  G11C2029/0411

Abstract: A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.

Abstract translation: 随机数发生器电路包括具有多个存储元件的第一存储器。 当由施加到第一存储器的电压源供电时，每个存储元件具有与之对应的初始状态。 第一存储器用于产生包括指示存储元件的相应初始状态的多个位的第一信号。 随机数发生器电路还包括耦合到第一存储器的纠错电路。 误差校正电路可操作以接收第一信号并且校正第一信号中的至少一个位，其在连续施加电力到第一存储器从而产生第二信号时不重复。 第二信号是在连续向第一存储器施加电力时可重复的随机数。

公开(公告)号：WO2009107267A1

公开(公告)日：2009-09-03

申请号：PCT/JP2008/067585

申请日：2008-09-19

Applicant: Kabushiki Kaisha Toshiba ,  YAMAGA, Akira

Inventor： YAMAGA, Akira

IPC: G06F12/16 ,  G11C16/04 ,  G11C16/06 ,  G11C29/42

CPC classification number: G06F11/1072 ,  G06F11/1012 ,  G06F11/1044 ,  G11C16/0483 ,  G11C2029/0411 ,  H03M13/29 ,  H03M13/2906

Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).

Abstract translation: 半导体存储装置，其控制方法和误差校正系统允许减少功耗和电路规模，而不损害纠错能力。 固态驱动器（SSD）的纠错码（ECC）电路使用第一纠错码（汉明码）对读取数据执行第一纠错，并且还使用第一纠错码（Hamming code）对第一纠错码的结果进行第二纠错 第二个纠错码（BHC码）。 此外，ECC电路使用第三纠错码（RS码）对第二纠错的结果进行第三纠错。

公开(公告)号：WO2009026696A1

公开(公告)日：2009-03-05

申请号：PCT/CA2008/001512

申请日：2008-08-27

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： OH, HakJune

IPC: G11C7/10 ,  G11C29/52

CPC classification number: G06F13/426 ,  G06F11/1068 ,  G06F13/1684 ,  G11C7/1006 ,  G11C2029/0411 ,  Y02D10/14 ,  Y02D10/151

Abstract: Daisy-chain memory configuration and usage is disclosed. According to one configuration, a memory system includes a controller and corresponding string of multiple successive memory devices coupled in a daisy-chain manner. The controller communicates commands over the serial control link to configure a first memory device to write a block of data to a second memory device in the chain. For example, the controller initiates copying a block of data by communicating over the daisy-chain control link to configure a first memory device of the multiple memory devices to be a source for outputting data, communicating over the daisy-chain control link to configure a second memory device to be a destination for receiving data, and communicating over the daisy-chain control link to initiate a transfer of the data from the first memory device to the second memory device.

Abstract translation: 公开了菊花链存储器配置和使用。 根据一种配置，存储器系统包括以菊花链方式耦合的控制器和多个连续存储器件的对应串。 控制器通过串行控制链路传送命令以配置第一存储器设备以将数据块写入链中的第二存储器设备。 例如，控制器通过菊花链控制链路进行通信来启动复制数据块，以将多个存储器件的第一存储器件配置为用于输出数据的源，通过菊花链控制链路进行通信以配置 第二存储器设备成为用于接收数据的目的地，以及通过菊花链控制链路进行通信，以启动数据从第一存储设备传输到第二存储设备。

公开(公告)号：WO2008156238A1

公开(公告)日：2008-12-24

申请号：PCT/KR2008/000128

申请日：2008-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： PARK, Sung Chung ,  KONG, Jun Jin ,  SONG, Seung-Hwan ,  KANG, Dong Ku

IPC: G11C16/26

CPC classification number: G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/0411

Abstract: A method and apparatus for controlling a reading level of a memory cell are provided. The method of controlling a reading level of a memory cell may include: receiving metric values calculated based on given voltage levels and reference levels; generating summed values for each of the reference levels by summing metric values corresponding to levels of a received signal from among the received metric values; selecting the reference level having the greatest value of the generated summed values from the reference levels; and controlling the reading level of the memory cell based on the selected reference level.

Abstract translation: 提供了一种用于控制存储单元的读取电平的方法和装置。 控制存储器单元的读取电平的方法可以包括：接收基于给定电压电平和参考电平计算出的度量值; 通过对应于来自接收到的度量值中的接收信号的电平的度量值相加来产生每个参考电平的相加值; 从所述参考电平中选择具有所生成的总和值的最大值的参考电平; 以及基于所选择的参考电平来控制所述存储器单元的读取电平。

公开(公告)号：WO2008100529A3

公开(公告)日：2008-11-27

申请号：PCT/US2008001882

申请日：2008-02-12

Applicant: MARVELL WORLD TRADE LTD ,  YANG XUESHI ,  WU ZINING ,  SUTARDJA PANTAS

Inventor： YANG XUESHI ,  WU ZINING ,  SUTARDJA PANTAS

IPC: G06F11/10 ,  G11C29/00

CPC classification number: G06F11/1068 ,  G11C29/18 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5002

Abstract: A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison.

Abstract translation: 存储器控制模块包括格式化模块，该格式化模块与包括B个存储器块的存储器阵列通信，每个B存储器块包括P个物理页面和Q个逻辑页面。 格式模块选择X个预定位置以在每个B存储块中写入导频数据和回读导频信号。 B，P，Q和X是大于或等于1的整数。存储器控制模块还包括信号处理模块，其将写入的导频数据与回读的导频信号进行比较，并确定写入的导频数据与 基于比较的回读导频信号。

公开(公告)号：WO2007025817A3

公开(公告)日：2007-05-03

申请号：PCT/EP2006064800

申请日：2006-07-28

Applicant: BOSCH GMBH ROBERT ,  WEIBERLE REINHARD ,  BOEHL EBERHARD

Inventor： WEIBERLE REINHARD ,  BOEHL EBERHARD

IPC: G06F11/07 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1008 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0401 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: In order to improve the availability of a data processing system in spite of possible memory errors, the inventive method consists in verifying a dataword readout with the aid of redundant additional information, when the data word is extracted from a memory cell (SO) and, if the data word is falsified, in carrying out an error treatment process which makes it possible to verify (S1-S3) the operability of the memory cell and, in the case when said memory cell is operable, the content thereof (S1-S3) is again produced.

Abstract translation: 为了改进数据处理系统的可用性，尽管可能的存储器错误，而从存储单元（SO）被检查读取的数据字，基于冗余附加信息的数据字的完整性; 并且，所述数据字被发现损坏，运行的错误处理过程，是在存储单元（S1-S3），并已检查的功能的情况下，如果存储器单元被发现是功能性的，它的内容（S7，S11）被恢复 ，

公开(公告)号：WO2003100791A1

公开(公告)日：2003-12-04

申请号：PCT/US2003/014975

申请日：2003-05-12

Applicant: SANDISK CORPORATION

Inventor： GUTERMAN, Daniel, C. ,  GROSS, Stephen, J. ,  GONGWER, Geoffrey, S.

IPC: G11C29/00

CPC classification number: G11C16/3418 ,  G06F11/1012 ,  G06F11/1072 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/3431 ,  G11C29/00 ,  G11C29/42 ,  G11C29/76 ,  G11C2029/0411

Abstract: The quality of data stored in a memory system in assessed by different methods, and the memory system is operated according to the assessed quality. The data quality (a) can be assessed during I-cad operations. Subsequent use of an Error Correction Code (a) can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption. In both cases the corrective actions can be implemented specifically on the poor quality data, according to suitably chosen schedules, and with improved effectiveness because of the knowledge provided by the quality indications. These methods can be especially useful in high-density memory systems constructed of multi-level storage memory cells.

Abstract translation: 存储在存储器系统中的数据的质量通过不同的方法评估，并且存储器系统根据评估的质量进行操作。 数据质量（a）可以在I-cad操作期间进行评估。 随后使用纠错码（a）可以利用质量指示来检测和重建数据，并提高效率。 或者，可以构建数据质量的统计，并且可以以修改的方式将数字数据值相关联以防止数据损坏。 在这两种情况下，根据适当选择的时间表，纠正措施可以针对质量差的数据进行具体实施，并且由于质量指示提供的知识而提高了效率。 这些方法对于由多级存储单元构成的高密度存储器系统尤其有用。

公开(公告)号：WO1994003901A1

公开(公告)日：1994-02-17

申请号：PCT/US1993007262

申请日：1993-08-05

Applicant: MONOLITHIC SYSTEM TECHNOLOGY, INC.

Inventor： MONOLITHIC SYSTEM TECHNOLOGY, INC. ,  LEUNG, Wing, Y. ,  HSU, Fu-Chieh

IPC: G11C29/00

CPC classification number: H04L25/0272 ,  G06F11/006 ,  G06F11/10 ,  G06F11/1032 ,  G06F11/2007 ,  G06F12/0661 ,  G06F13/4077 ,  G11C5/04 ,  G11C29/006 ,  G11C29/08 ,  G11C29/48 ,  G11C29/76 ,  G11C29/808 ,  G11C29/81 ,  G11C29/832 ,  G11C29/88 ,  G11C2029/0401 ,  G11C2029/0411 ,  G11C2029/4402 ,  H01L22/22 ,  H01L27/0203 ,  H04L5/1461 ,  H04L25/026 ,  H04L25/028 ,  H04L25/029 ,  H04L25/0292 ,  Y10S257/907

Abstract: A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the small bus; 5) use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) use of spare bus lines to provide local redundancy for the bus; and 9) use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.

Abstract translation: 容错的高速晶片秤系统包括多个功能模块，对互连网络中的缺陷容错的并行分层总线以及一个或多个总线主机。 该总线包括分段成多个总线线路，并通过互连网络中的可编程总线开关和总线收发器或中继器连接在一起。 通过：1）使用小块大小（512K位）作为内存模块; 2）使用可编程标识寄存器来促进动态地址映射并相对容易地整合全局冗余; 3）使用总线的网格结构为互连网络提供全局冗余; 4）使用由13条信号线组成的较窄的总线，以保持小型公共汽车的总面积; 5）使用由可编程开关和可编程总线收发器连接的分段总线，以便于轻松隔离总线缺陷; 6）使用专用电路进行总线收发器和异步握手，方便动态总线配置; 7）使用可编程控制寄存器，方便运行时总线重新配置; 8）使用备用总线为总线提供局部冗余; 和9）在存储器模块中使用备用行和列提供局部冗余，获得分层总线中的高缺陷容限。

公开(公告)号：WO2019106484A1

公开(公告)日：2019-06-06

申请号：PCT/IB2018/059116

申请日：2018-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： MEANEY, Patrick ,  JACOBI, Christian ,  TRAGER, Barry

IPC: G11C29/10

CPC classification number: G06F11/1068 ,  G06F11/108 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/1515

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.