中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

89 records (took 0.055 seconds)

    SYSTEM ON CHIP AND METHOD THEREFOR
    1.
    发明申请
    SYSTEM ON CHIP AND METHOD THEREFOR 审中-公开
    芯片系统及其方法

    公开(公告)号：WO2015008112A1

    公开(公告)日：2015-01-22

    申请号：PCT/IB2013/055907

    申请日：2013-07-18

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ROHLEDER, Michael ,  HAY, Gary ,  LUEDEKE, Thomas ,  MUELLER, Stephan

    Inventor： ROHLEDER, Michael ,  HAY, Gary ,  LUEDEKE, Thomas ,  MUELLER, Stephan

    IPC: G06F21/30 ,  G06F1/00

    CPC classification number: H04L63/101 ,  G06F1/00 ,  G06F21/30 ,  G06F21/60 ,  G06F21/70 ,  G06F21/78 ,  G06F21/79 ,  H04L63/08

    Abstract: A system on chip (10) comprises a responder unit (14) comprising a set of responder elements (15) and an access control unit (18) associated with an authorization list (38) and the responder unit (14). An entry of the authorization list (38) defines a set of access requirements in relation to an address space identifying at least part of the responder unit (14). The access control unit (18) is arranged to: receive a request for access (34) to a target responder element (15') among the responder elements (15) of the responder unit (14), determine the corresponding set of access requirements for the received access request from the authorization list (38), and evaluate the request for access (34) with respect to the determined set of access requirements and generate a first request evaluation result (56). A protection unit (36) associated with the responder unit (14) is arranged to: provide a group assignment (40) assigning a group (G1, G2, G3,...) to each of the responder elements (15) of the responder unit (14), provide a group authorization list (42), an entry of the group authorization list (42) defining a set of group access requirements for the group assigned, receive the request for access (34) to the target responder element (15'), determine the group assigned to the target responder element (15') from the group assignment (40) and further determine the set of group access requirements from the group authorization list (42) for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result (58). Interaction with the target responder element (15') is controlled in response to the first and/or second evaluation result (56, 58).

    Abstract translation: 片上系统（10）包括响应器单元（14），其包括一组应答器元件（15）和与授权列表（38）和响应器单元（14）相关联的访问控制单元（18）。 授权列表（38）的条目定义了与识别响应器单元（14）的至少一部分的地址空间相关的一组访问要求。 访问控制单元（18）被布置为：在应答器单元（14）的应答器元件（15）中接收对目标响应器元件（15'）的访问请求（34），确定相应的访问要求集合 对于来自授权列表（38）的接收到的访问请求，并且针对所确定的访问要求集合来评估对访问请求（34），并且生成第一请求评估结果（56）。 与响应器单元（14）相关联的保护单元（36）被布置成：提供将组（G1，G2，G3，...）分配给每个应答器元件（15）的组分配（40） 响应器单元（14）提供组授权列表（42），组授权列表（42）的条目定义为所分组的组的访问要求的集合，接收对目标应答器元素（34）的请求 （15'），从组分配（40）确定分配给目标响应者元素（15'）的组，并且进一步根据所分组的组的授权列表（42）确定组访问要求的集合。 片上系统还评估关于所确定的组访问要求集合的请求，并产生第二请求评估结果（58）。 响应于第一和/或第二评估结果（56,58）来控制与目标响应元件（15'）的相互作用。

    MEMORY SYSTEM WITH REDUNDANT DATA STORAGE AND ERROR CORRECTION
    3.
    发明申请
    MEMORY SYSTEM WITH REDUNDANT DATA STORAGE AND ERROR CORRECTION 审中-公开
    具有冗余数据存储和错误校正的存储器系统

    公开(公告)号：WO2009153623A1

    公开(公告)日：2009-12-23

    申请号：PCT/IB2008/052447

    申请日：2008-06-20

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ROHLEDER, Michael ,  HAY, Gary ,  MUELLER, Stephan ,  THANNER, Manfred

    Inventor： ROHLEDER, Michael ,  HAY, Gary ,  MUELLER, Stephan ,  THANNER, Manfred

    IPC: G11C29/00 ,  G06F11/16

    CPC classification number: G06F11/167 ,  G11C29/74 ,  G11C2029/0411

    Abstract: A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RA M routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from th e at least two RAM elements and provide an error indication signal to the RAM routing logic in re sponse thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of t he redundant data and the error indication signal.

    Abstract translation: 系统包括被布置为冗余地存储数据的至少两个随机存取存储器（RAM）元件。 系统还包括RA M路由逻辑，其包括可操作地耦合到所述至少两个RAM元素的比较逻辑，并且被布置为比较与所述至少两个RAM元素读取的冗余数据，以及独立于所述RAM路由逻辑的检查和验证逻辑， 至少两个RAM元件，并且被布置为附加地检测从至少两个RAM元件读取的冗余数据中的错误，并向RAM路由逻辑提供错误指示信号以对其进行响应。 RAM路由逻辑还包括选择逻辑，其被布置为基于冗余数据和错误指示信号的比较来动态地从至少两个RAM元素中的一个RAM元素中选择冗余数据。

    PROCESSOR BASED SYSTEM HAVING ECC BASED CHECK AND ACCESS VALIDATION INFORMATION MEANS
    5.
    发明申请
    PROCESSOR BASED SYSTEM HAVING ECC BASED CHECK AND ACCESS VALIDATION INFORMATION MEANS 审中-公开
    基于ECC的基于处理器的系统检查和访问验证信息手段

    公开(公告)号：WO2009090502A1

    公开(公告)日：2009-07-23

    申请号：PCT/IB2008/050149

    申请日：2008-01-16

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  ROHLEDER, Michael ,  HAY, Gary ,  MUELLER, Stephan ,  THANNER, Manfred

    Inventor： ROHLEDER, Michael ,  HAY, Gary ,  MUELLER, Stephan ,  THANNER, Manfred

    IPC: G06F11/00 ,  G06F12/14

    CPC classification number: G06F11/1645 ,  G06F11/10 ,  G06F11/1654 ,  G06F2201/845

    Abstract: A system (100) comprises a first master element (110, 910); and at least one shared communication element (130, 940) arranged to operably couple the first master element (110, 910) to at least one slave element (140, 150, 170). The system (100) further comprises at least one validation element (180, 190, 960, 970, 980, 990) located on at least one further validation path (114, 124, 117) located between the first master element (110, 910) and the at least one slave element (140, 150, 170), wherein the at least one validation element (180, 190, 960, 970, 980, 990) is arranged to validate at least one of: at least one access request by the first master element (110, 910); and a response to an access request from the at least one slave element (140, 150, 170).

    Abstract translation: 系统（100）包括第一主元件（110,910）; 以及布置成可操作地将第一主元件（110,910）耦合到至少一个从属元件（140,150,170）的至少一个共享通信元件（130,940）。 所述系统（100）还包括至少一个确定元件（180,190,960,970,980,990），位于所述第一主元件（110,910）之间的至少一个另外的验证路径（114,124,117）上， ）和所述至少一个从属元件（140,150,170），其中所述至少一个验证元件（180,190,990,970,980,990）被布置成验证以下至少一个：至少一个访问请求 通过第一主元件（110,910）; 以及对来自所述至少一个从属元件（140,150,170）的访问请求的响应。

Patent Agency Ranking