公开(公告)号：WO0120646A3

公开(公告)日：2002-02-21

申请号：PCT/US0024426

申请日：2000-09-06

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHULZE STEFFEN ,  VARIAN KATHRYN H ,  WILTSHIRE TIMOTHY

IPC: G03F7/20 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/544 ,  H01L21/306

CPC classification number: G03F7/70633 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various fill strategies in the optical kerf are provided. A semiconductor wafer is divided into chip areas by strips of optical kerf regions. The optical kerf regions contain alignment marks used in the lithography processes. Partial fill patterns are provided in the optical kerf regions so that the area factor of the kerf region is similar to that of the chip areas. This results in full planarization by chemical mechanical polishing becoming feasible. Additionally, the fill is patterned so the alignment marks may be read accurately.

Abstract translation: 提供了光学切口中的各种填充策略。 半导体晶片通过光学切口区域的条带分成芯片区域。 光学切口区域包含在光刻工艺中使用的对准标记。 在光学切口区域中提供部分填充图案，使得切口区域的面积因子类似于芯片区域的面积因子。 这导致通过化学机械抛光的完全平坦化变得可行。 此外，填充物被图案化，使得对准标记可以被准确地读取。

公开(公告)号：WO0124234A3

公开(公告)日：2002-01-17

申请号：PCT/US0027139

申请日：2000-09-28

Applicant: LAM RES CORP

Inventor： MIKHAYLICH KATRINA A ,  RAVKIN MIKE

IPC: C11D7/06 ,  C09K13/08 ,  C11D7/18 ,  C11D7/26 ,  C11D7/32 ,  C11D7/60 ,  C11D17/08 ,  H01L21/02 ,  H01L21/304 ,  H01L21/321 ,  H01L21/306

CPC classification number: H01L21/02074 ,  Y10S134/902

Abstract: A method is provided for cleaning a surface of a semiconductor wafer after a CMP operation. In one example, an improved cleaning chemical (ICC) is applied to the surface of the wafer. The ICC is configured to transform a copper film on the surface of the wafer into a water soluble form. The wafer surface is scrubbed. The wafer is then rinsed with a liquid. The scrubbing and the rinsing are configured to remove a controlled amount of the water soluble copper from the surface of the wafer and the brush, wherein the applying, the scrubbing, and the rinsing are performed in a brush box.

Abstract translation: 提供了一种在CMP操作之后清洁半导体晶片的表面的方法。 在一个示例中，将改进的清洁化学品（ICC）施加到晶片的表面。 ICC被配置为将晶片表面上的铜膜转化成水溶性形式。 晶片表面被擦洗。 然后用液体冲洗晶片。 洗涤和冲洗被配置为从晶片和刷子的表面去除受控量的水溶性铜，其中施加，洗涤和漂洗在刷盒中进行。

公开(公告)号：WO01088972A1

公开(公告)日：2001-11-22

申请号：PCT/FI2001/000473

申请日：2001-05-15

IPC: H01L21/285 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/321

CPC classification number: H01L21/76843 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76823 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76886 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/12044 ,  H01L2924/00 ,  H01L2924/01005

Abstract: This invention concerns a process for producing integrated circuits containing at least one layer of elemental metal which during the processing of the integrated circuit is at least partly in the form of metal oxide, and the use of an organic compound containing certain functional groups for the reduction of a metal oxide layer formed during the production of an integrated circuit. According to the present process the metal oxide layer is at least partly reduced to elemental metal with a reducing agent selected from organic compounds containing one or more of the following functional groups: alcohol (-OH), aldehyde (-CHO), and carboxylic acid (-COOH).

Abstract translation: 本发明涉及一种制造集成电路的方法，该集成电路包含至少一层元素金属，其在集成电路的处理期间至少部分为金属氧化物的形式，并且使用含有某些官能团的有机化合物进行还原 在制造集成电路期间形成的金属氧化物层。 根据本发明方法，金属氧化物层至少部分还原成还原剂，还原剂选自含有一个或多个下列官能团的有机化合物：醇（-OH），醛（-CHO）和羧酸 （-COOH）。

公开(公告)号：WO01088229A1

公开(公告)日：2001-11-22

申请号：PCT/US2001/014652

申请日：2001-05-03

IPC: C25F3/22 ,  C25F7/00 ,  H01L21/321 ,  H01L21/768 ,  C25F3/30

CPC classification number: C25F3/22 ,  C25F7/00 ,  H01L21/32115 ,  H01L21/7684

Abstract: An apparatus for detecting the end-point of an electropolishing process of a metal layer formed on a wafer (1004) includes an end-point detector. The end-point detector is disposed adjacent the nozzle (1008) used to electropolish the wafer. In one embodiment, the end-point detector is configured to measure the optical reflectivity of the portion of the wafer being electropolished.

Abstract translation: 用于检测形成在晶片（1004）上的金属层的电解抛光工艺的端点的装置包括端点检测器。 端点检测器设置在用于电抛光晶片的喷嘴（1008）附近。 在一个实施例中，端点检测器被配置为测量被电抛光的晶片的部分的光学反射率。

公开(公告)号：WO01084605A1

公开(公告)日：2001-11-08

申请号：PCT/EP2001/004786

申请日：2001-04-27

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L28/55 ,  H01L21/31053 ,  H01L21/3212 ,  H01L28/60 ,  H01L28/75 ,  H01L28/90

Abstract: The invention relates to a method for producing at least one capacitor structure, comprising the following steps: providing a substrate, producing a first electrode on said substrate, producing a mask, whereby the first electrode is disposed in an opening of said mask, and applying at least one dielectric layer and at least one conductive layer for a second electrode. The surface of the part of the conductive layer that is applied in the opening of the mask is substantially disposed below the surface of the mask. The conductive layer and the dielectric layer are structured by polishing so that a capacitor structure is produced.

Abstract translation: 根据提供了一种用于产生至少一个电容器结构，包括下列步骤的方法的本发明：提供基板，形成在基板上的第一电极，掩模生成，其中，所述第一电极设置在掩模的开口中，至少一个介电层 和用于第二电极的至少一个导电层被施加，其特征在于，在所述掩模的开口施加的，基本上低于掩模设置的表面，并通过抛光所述导电层，所述导电层和所述电介质的所述部分的表面 图案化的层，从而使电容器结构被产生。

公开(公告)号：WO01078135A2

公开(公告)日：2001-10-18

申请号：PCT/US2001/009500

申请日：2001-03-22

IPC: H01L21/288 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76892

Abstract: The present invention relates to methods for repairing defects (8, 10) on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions (8) in the cavities while removing residual portions (10) from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden (7) on a top surface of the substrate. The present invention also disclosed a method for depositing a second conductive material on the first conductive material of the substrate.

Abstract translation: 本发明涉及在半导体衬底上修复缺陷（8,10）的方法。 这是通过选择性地将导电材料沉积在空腔中的缺陷部分（8）中，同时从衬底的场区域移除残余部分（10）来实现的。 根据本发明的另一种方法包括在衬底的顶表面上形成均匀的导电材料覆盖层（7）。 本发明还公开了一种在衬底的第一导电材料上沉积第二导电材料的方法。

公开(公告)号：WO01071789A1

公开(公告)日：2001-09-27

申请号：PCT/JP2001/002148

申请日：2001-03-19

IPC: C11D7/26 ,  C11D7/32 ,  C11D7/34 ,  C11D11/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/321 ,  H01L21/768 ,  H01L21/304

CPC classification number: H01L21/02074 ,  C11D7/265 ,  C11D7/3209 ,  C11D7/3245 ,  C11D7/3272 ,  C11D7/34 ,  C11D11/0047 ,  C23G1/20 ,  H01L21/76877

Abstract: A semiconductor surface cleaning agent containing a compound the molecule of which has a nitrogen atom having an unshared electron pair and used for cleaning the surface of a semiconductor on which copper wiring is provided, and a method for cleaning the surface of a semiconductor characterized by treating the surface of a semiconductor on which copper wiring is provided with such a cleaning agent. The cleaning agent does not corrode the copper wiring (copper thin film) on the semiconductor and SiO2 of the interlayer insulating film, does not impair the flatness of the surface, and is effective in removing CuO and particles adhering to the surface at the Cu-CMP step.

Abstract translation: 一种半导体表面清洁剂，其含有其分子具有具有未共享电子对的氮原子并用于清洁其上提供铜布线的半导体的表面的化合物，以及用于清洁半导体表面的方法，其特征在于， 铜布线上设置有这种清洁剂的半导体的表面。 清洗剂不会腐蚀半导体上的铜布线（铜薄膜）和层间绝缘膜的SiO 2，不损害表面的平坦度，有效地除去CuO和附着在Cu- CMP步骤。

公开(公告)号：WO01061739A1

公开(公告)日：2001-08-23

申请号：PCT/EP2001/000715

申请日：2001-01-23

IPC: H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/32137 ,  H01L21/32115 ,  H01L21/763 ,  H01L28/20

Abstract: The invention is directed to a process for forming a recess in at least one poly silicon overfilled trench in an integrated circuit, comprising the following steps: uniformly etching the poly silicon overfill layer (4); stopping the etching before the poly silicon layer (4) is completely removed from the surface of the integrated circuit; and recess etching the polysilicon layer (4) with microtrenching properties for forming a substantially planar recess (6) near the top of the at least one trench (3).

Abstract translation: 本发明涉及一种用于在集成电路中的至少一个多晶硅过填充沟槽中形成凹陷的方法，包括以下步骤：均匀蚀刻多晶硅填充层（4）; 在多晶硅层（4）从集成电路的表面完全去除之前停止蚀刻; 以及用微凹槽性质凹陷蚀刻所述多晶硅层（4），用于在所述至少一个沟槽（3）的顶部附近形成基本平坦的凹部（6）。

公开(公告)号：WO01060242A2

公开(公告)日：2001-08-23

申请号：PCT/IL2001/000160

申请日：2001-02-20

IPC: B24B37/04 ,  B24B49/12 ,  B24B49/14 ,  H01L21/321 ,  H01L23/544 ,  A61B5/00

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  B24B49/14 ,  H01L21/3212 ,  H01L22/34

Abstract: A test structure is presented to be formed on a patterned structure and to be used for controlling a CMP process applied to the patterned structure, which has a pattern area formed by spaced-apart metal-containing regions representative of real features of the patterned structure. The test structure thus undergoes the same CMP processing as the pattern area. The test structure comprises at least two structures aligned along a vertical axis in a spaced-apart parallel relationship, each structure comprising at least one pattern zone containing spaced-apart metal regions, the test structure thereby comprising at least one pair of vertically aligned upper and lower pattern zones. The upper and lower pattern zones in each pair have different patterns oriented with respect to each other such that the metal regions of the lower pattern are located underneath the spaces between the metal regions of the upper pattern.

Abstract translation: 呈现在图案化结构上形成的测试结构，并且用于控制施加到图案化结构的CMP工艺，其具有由表示图案化结构的实际特征的间隔开的含金属区域形成的图案区域。 因此，测试结构经历与图案区域相同的CMP处理。 测试结构包括至少两个以垂直轴线间隔开的平行关系对准的结构，每个结构包括至少一个包含间隔开的金属区域的图案区域，测试结构由此包括至少一对垂直对准的上部和 较低的图案区域。 每对中的上图案区和下图案区具有相对于彼此定向的不同图案，使得下图案的金属区域位于上图案的金属区域之间的空间的下方。

公开(公告)号：WO01057919A1

公开(公告)日：2001-08-09

申请号：PCT/JP2001/000774

申请日：2001-02-02

IPC: C09G1/02 ,  C09K3/14 ,  H01L21/321 ,  H01L21/304

CPC classification number: C09G1/02 ,  C09K3/1436 ,  C09K3/1463 ,  H01L21/3212

Abstract: A polishing composite for LSI manufacture is provided that, adjusted to pH 5.5-9.0 by alkaline substance, includes water, abrasive, organic acid and oxidizer, so that a barrier metal of Ta or TaN (4) and a copper wiring layer (6) can be polished at higher speed while preventing dishing and erosion. The composite is used for polishing a copper-base wiring layer (6) that comprises copper (5a, 5b, 6) deposited on a barrier metal (4) consisting of Ta and TaN over insulating film (2).

Abstract translation: 提供一种用于LSI制造的抛光复合体，其通过碱性物质调节至pH 5.5-9.0，包括水，研磨剂，有机酸和氧化剂，使得Ta或TaN（4）和铜布线层（6）的阻挡金属， 可以更高速度抛光，同时防止凹陷和侵蚀。 该复合体用于抛光沉积在由Ta和TaN组成的阻挡金属（4）上的绝缘膜（2）上的铜（5a，5b，6）的铜基布线层（6）。