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    METAL-DOPED BORON FILMS
    71.
    发明申请
    METAL-DOPED BORON FILMS 审中-公开

    公开(公告)号：WO2022231886A1

    公开(公告)日：2022-11-03

    申请号：PCT/US2022/025281

    申请日：2022-04-19

    Applicant: APPLIED MATERIALS, INC.

    Inventor： AYDIN, Aykut ,  CHENG, Rui ,  JANAKIRAMAN, Karthik

    IPC: H01L21/02 ,  H01L21/311 ,  H01L21/033

    Abstract: Exemplary deposition methods may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the boron-containing precursor. The dopant-containing precursor may include a metal. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a doped-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The doped-boron material may include greater than or about 80 at.% of boron in the doped-boron material.

    DIRECT LIFT CATHODE FOR LITHOGRAPHY MASK CHAMBER
    72.
    发明申请
    DIRECT LIFT CATHODE FOR LITHOGRAPHY MASK CHAMBER 审中-公开

    公开(公告)号：WO2022231829A1

    公开(公告)日：2022-11-03

    申请号：PCT/US2022/024222

    申请日：2022-04-11

    Applicant: APPLIED MATERIALS, INC.

    Inventor： NGUYEN, Khiem

    IPC: G03F1/80 ,  H01L21/687

    Abstract: Exemplary lithography mask processing chambers may include a substrate support that includes a plurality of lift pins that are vertically translatable relative to a top surface of the substrate support. The lithography mask processing chambers may include a cover ring positioned atop the substrate support. The cover ring may define a rectilinear substrate seat. A top surface of the rectilinear substrate seat may be elevated above the top surface of the substrate support. An outer periphery of the rectilinear substrate seat may be positioned outward of the plurality of lift pins.

    PLASMA ETCHING OF MASK MATERIALS
    73.
    发明申请
    PLASMA ETCHING OF MASK MATERIALS 审中-公开

    公开(公告)号：WO2022231815A1

    公开(公告)日：2022-11-03

    申请号：PCT/US2022/023782

    申请日：2022-04-07

    Applicant: APPLIED MATERIALS, INC.

    Inventor： LEUNG, Toi Yue Becky ,  CHANDRACHOOD, Madhavi Rajaram ,  YALAMANCHILI, Madhava Rao

    IPC: G03F1/80 ,  G03F1/22

    Abstract: Exemplary etching methods may include forming a plasma of a fluorine-containing precursor to produce plasma effluents. A first bias frequency may be applied while forming the plasma. The methods may include contacting a substrate housed in a processing region of a semiconductor processing chamber with the plasma effluents. The substrate may be or include a photomask. The methods may include etching a first layer of the photomask. Etching the first layer of the photomask may expose a second layer of the photomask. The methods may include adjusting the first bias frequency to a second bias frequency while maintaining the plasma of the fluorine-containing precursor. The methods may include etching the second layer of the photomask.

    SELECTIVE REMOVAL OF RUTHENIUM-CONTAINING MATERIALS
    74.
    发明申请
    SELECTIVE REMOVAL OF RUTHENIUM-CONTAINING MATERIALS 审中-公开

    公开(公告)号：WO2022231814A1

    公开(公告)日：2022-11-03

    申请号：PCT/US2022/023776

    申请日：2022-04-07

    Applicant: APPLIED MATERIALS, INC.

    Inventor： WANG, Baiwei ,  CHEN, Xiaolin C. ,  REDDY, Rohan Puligoru ,  JAN, Oliver ,  CUI, Zhenjiang ,  WANG, Anchuan

    IPC: H01L21/3213 ,  H01L21/02

    Abstract: Exemplary etching methods may include flowing an oxygen-containing precursor into a processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the processing region with the oxygen-containing precursor. The substrate may include an exposed region of ruthenium, and the contacting may produce ruthenium tetroxide. The methods may include vaporizing the ruthenium tetroxide from a surface of the exposed region of ruthenium. An amount of oxidized ruthenium may remain. The methods may include contacting the oxidized ruthenium with a hydrogen-containing precursor. The methods may include removing the oxidized ruthenium.

    PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER
    75.
    发明申请
    PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER 审中-公开

    公开(公告)号：WO2022231760A1

    公开(公告)日：2022-11-03

    申请号：PCT/US2022/022988

    申请日：2022-04-01

    Applicant: APPLIED MATERIALS, INC.

    Inventor： SHEN, Zeqing ,  QI, Bo ,  MALLICK, Abhijit B.

    IPC: H01L21/311 ,  H01L27/112

    Abstract: Embodiments of the present disclosure generally relate to fabricating electronic devices, such as memory devices. In one or more embodiments, a method for forming a device includes forming a film stack on a substrate, where the film stack contains a plurality of alternating layers of oxide layers and nitride layers and has a stack thickness, and etching the film stack to a first depth to form a plurality of openings between a plurality of structures. The method includes depositing an etch protection liner containing amorphous-silicon on the sidewalls and the bottoms of the structures, removing the etch protection liner from at least the bottoms of the openings, forming a plurality of holes by etching the film stack in the openings to further extend each bottom of the openings to a second depth of the hole, and removing the etch protection liner from the sidewalls.

    IN-SITU FILM GROWTH RATE MONITORING APPARATUS, SYSTEMS, AND METHODS FOR SUBSTRATE PROCESSING
    76.
    发明申请
    IN-SITU FILM GROWTH RATE MONITORING APPARATUS, SYSTEMS, AND METHODS FOR SUBSTRATE PROCESSING 审中-公开

    公开(公告)号：WO2022231671A1

    公开(公告)日：2022-11-03

    申请号：PCT/US2022/013259

    申请日：2022-01-21

    Applicant: APPLIED MATERIALS, INC.

    Inventor： CONG, Zhepeng ,  MYO, Nyi O. ,  SHENG, Tao ,  ZHENG, Yong

    IPC: G01B11/06 ,  C30B25/16 ,  C30B29/58

    Abstract: Embodiments of the present disclosure generally relate to apparatus, systems, and methods for in-situ film growth rate monitoring. A thickness of a film on a substrate is monitored during a substrate processing operation that deposits the film on the substrate. The thickness is monitored while the substrate processing operation is conducted, The monitoring includes directing light in a direction toward a crystalline coupon, The direction is perpendicular to a heating direction. In one implementation, a reflectometer system to monitor film growth during substrate processing operations includes a first block that includes a first inner surface. The reflectometer system includes a light emitter disposed in the first block and oriented toward the first inner surface, and a light receiver disposed in the first block and oriented toward the first inner surface. The reflectometer system includes a second block opposing the first block.

    THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY (3D DRAM) GATE ALL-AROUND (GAA) DESIGN USING STACKED SI/SIGE
    77.
    发明申请
    THREE-DIMENSIONAL DYNAMIC RANDOM-ACCESS MEMORY (3D DRAM) GATE ALL-AROUND (GAA) DESIGN USING STACKED SI/SIGE 审中-公开

    公开(公告)号：WO2022226236A1

    公开(公告)日：2022-10-27

    申请号：PCT/US2022/025831

    申请日：2022-04-21

    Applicant: APPLIED MATERIALS, INC.

    Inventor： VARGHESE, Sony ,  FISHBURN, Fredrick David

    IPC: H01L27/108 ,  H01L29/423

    Abstract: Methods of forming a three-dimensional dynamic random-access memory (3D DRAM) structure are provided herein. In some embodiments, a method of forming a 3D DRAM structure includes forming at least one wordline feature in a first stack comprising a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, wherein the wordline feature comprises: vertically etching a first pattern of holes; filling the first pattern of holes with a silicon germanium fill; vertically etching a plurality of isolation slots through the first stack; filling the plurality of isolation slots with a dielectric material to form an isolation layer between the silicon germanium fill; etching the silicon germanium fill and the plurality of c-SiGe layers to form a plurality of gate silicon channels comprising portions of the plurality of c-Si layers; and depositing a layer of conductive material that wraps around the plurality of gate silicon channels.

    CONDUCTIVE OXIDE OVERHANG STRUCTURES FOR OLED DEVICES
    78.
    发明申请
    CONDUCTIVE OXIDE OVERHANG STRUCTURES FOR OLED DEVICES 审中-公开

    公开(公告)号：WO2022225657A1

    公开(公告)日：2022-10-27

    申请号：PCT/US2022/022191

    申请日：2022-03-28

    Applicant: APPLIED MATERIALS, INC.

    Inventor： CHOUNG, Ji-young ,  CHEN, Chung-Chia ,  LIN, Yu Hsin ,  LEE, Jungmin ,  HAAS, Dieter ,  KIM, Si Kyoung

    IPC: H01L27/32 ,  H01L51/52

    Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in an organic light-emitting diode (OLED) display are described herein. The overhang structures are permanent to the sub-pixel circuit. The overhang structures include a conductive oxide. A first configuration of the overhang structures includes a base portion and a top portion with the top portion disposed on the base portion. In a first sub-configuration, the base portion includes the conductive oxide of at least one of a TCO material or a TMO material. In a second sub-configuration, the base portion includes a metal alloy material and the conductive oxide of a metal oxide surface. A second configuration of the overhang structures includes the base portion and the top portion with a body portion disposed between the base portion and the top portion. The body portion includes the metal alloy body and the metal oxide surface.

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