公开(公告)号：WO2009108562A3

公开(公告)日：2009-11-12

申请号：PCT/US2009034486

申请日：2009-02-19

Applicant: RAMBUS INC ,  ABBASFAR ALIAZAM

Inventor： ABBASFAR ALIAZAM

IPC: G06F11/10

CPC classification number: G06F11/08 ,  G06F11/0793 ,  G06F11/1004

Abstract: Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error- detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Furthermore, control logic performs remedial action based on the feedback information.

Abstract translation: 描述电路的实施例。 在该电路中，编码器电路将一组N个符号编码为代码空间中的给定码字，其中给定码字包括一组M个符号。 M个驱动器耦合到编码器电路并且耦合到信道中的M个链路，其中给定的驱动器将M个符号集合中的给定符号输出到给定的链路上。 此外，耦合到编码器电路的错误检测电路产生并存储与该M个符号组相关联的错误检测信息，其中错误检测信息有助于在通信期间的错误类型的随后概率确定 一组M符号到另一个电路。 此外，接收器电路从另一电路接收反馈信息。 该反馈信息包括关于基于代码空间的特征来检测M个符号集合中的另一种类型的错误的错误信息。 此外，控制逻辑基于反馈信息执行补救动作。

公开(公告)号：WO2009111175A1

公开(公告)日：2009-09-11

申请号：PCT/US2009/034494

申请日：2009-02-19

Applicant: RAMBUS INC. ,  KIZER, Jade, M. ,  WILSON, John ,  LUO, Lei ,  WARE, Frederick ,  ZERBE, Jared, L.

Inventor： KIZER, Jade, M. ,  WILSON, John ,  LUO, Lei ,  WARE, Frederick ,  ZERBE, Jared, L.

IPC: H04L25/49

CPC classification number: H03M13/47 ,  H04L25/4919

Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

Abstract translation: 描述电路的实施例。 在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。 此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。 另外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡，以及M个符号集合中的第二值的多个实例，并且如果不平衡是 检测到，这会导致错误条件。

公开(公告)号：WO2009111174A1

公开(公告)日：2009-09-11

申请号：PCT/US2009/034491

申请日：2009-02-19

Applicant: RAMBUS INC. ,  HAUKNESS, Brent, S. ,  SHAEFFER, Ian ,  BRONNER, Gary, B.

Inventor： HAUKNESS, Brent, S. ,  SHAEFFER, Ian ,  BRONNER, Gary, B.

IPC: G11C16/14 ,  G11C16/16

CPC classification number: G11C16/16

Abstract: Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device.

Abstract translation: 描述电路的实施例。 该电路包括产生多个分段擦除命令的控制逻辑，以擦除存储在另一个电路内形成的存储器件的存储单元中的信息。 注意，在存储器件内执行多个分段擦除命令中的单个擦除命令可能不足以擦除存储在存储单元中的信息。 此外，第一电路包括从控制逻辑接收多个分段擦除命令并将多个分段擦除命令发送到存储器件的接口。

公开(公告)号：WO2009108562A2

公开(公告)日：2009-09-03

申请号：PCT/US2009/034486

申请日：2009-02-19

Applicant: RAMBUS INC. ,  ABBASFAR, Aliazam

Inventor： ABBASFAR, Aliazam

IPC: H03M13/00

CPC classification number: G06F11/08 ,  G06F11/0793 ,  G06F11/1004

Abstract: Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error- detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Furthermore, control logic performs remedial action based on the feedback information.

Abstract translation: 描述了电路的实施例。 在该电路中，编码器电路将一组N字符编码为代码空间中的给定码字，其中该给定码字包括一组M symbols个符号。 M个驱动器耦合到编码器电路并且耦合到通道中的M个链路，其中给定的驱动器输出该组M中的给定符号， 我>符号到给定的链接。 此外，耦合到编码器电路的错误检测电路产生并存储与该组M个符号相关的错误检测信息，其中错误检测信息有助于后续的概率性确定 在将该组M个符号传送到另一个电路期间的错误类型。 另外，接收器电路从另一个电路接收反馈信息。 该反馈信息包括关于根据代码空间的特征检测该组符号中的另一种类型的错误的错误信息。 此外，控制逻辑基于反馈信息执行补救行动。

公开(公告)号：WO2009086433A3

公开(公告)日：2009-08-27

申请号：PCT/US2008088255

申请日：2008-12-23

Applicant: RAMBUS INC ,  BRONNER GARY BELA

Inventor： BRONNER GARY BELA

IPC: H01L21/28 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7884 ,  H01L29/7923

Abstract: A non-volatile memory cell includes a charge storage layer formed in a groove in a semiconductor substrate, and a source region and a drain region on opposite sides of the groove, with at least part of the charge storage layer not overlapping with the source region and the drain region. The non-volatile memory cell may be a flash memory cell or a SONOS type memory cell.

Abstract translation: 非易失性存储单元包括形成在半导体衬底中的沟槽中的电荷存储层，以及沟槽相对侧上的源极区域和漏极区域，电荷存储层的至少一部分不与源极区域重叠 和漏极区域。 非易失性存储单元可以是闪存单元或SONOS型存储单元。

公开(公告)号：WO2009058790A1

公开(公告)日：2009-05-07

申请号：PCT/US2008/081478

申请日：2008-10-28

Applicant: RAMBUS INC. ,  LIN, Qi ,  LEE, Hae-Chang ,  KIM, Jaeha ,  LEIBOWITZ, Brian, S. ,  ZERBE, Jared, L. ,  REN, Jihong

Inventor： LIN, Qi ,  LEE, Hae-Chang ,  KIM, Jaeha ,  LEIBOWITZ, Brian, S. ,  ZERBE, Jared, L. ,  REN, Jihong

IPC: H04L5/20

CPC classification number: H04L25/0272 ,  H04L5/20 ,  H04L25/0262

Abstract: A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,- the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.

Abstract translation: 数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。 第一和第二相应的传输线包括数据接收器电路外部的一对传输线。 第一和第二接口从一对传输线接收传输信号。 共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。 差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。 所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。 差分模式电路与提取的时钟信号同步。

公开(公告)号：WO2009058789A1

公开(公告)日：2009-05-07

申请号：PCT/US2008/081477

申请日：2008-10-28

Applicant: RAMBUS INC. ,  LIN, Qi ,  KIM, Jaeha ,  LEIBOWITZ, Brian, S. ,  ZERBE, Jared, L. ,  REN, Jihong

Inventor： LIN, Qi ,  KIM, Jaeha ,  LEIBOWITZ, Brian, S. ,  ZERBE, Jared, L. ,  REN, Jihong

IPC: H04L7/027 ,  H04L7/00

CPC classification number: H04L7/0008 ,  H04L7/065 ,  H04L25/0276 ,  H04L25/14

Abstract: A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.

Abstract translation: 数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。 数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。 第一速率是第二速率的倍数，其中倍数大于1。 数据传输电路还包括与符号时钟同步的数据驱动器。 数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。 数据信号和时钟信号同时被驱动到一个或多个传输线上。

公开(公告)号：WO2009055150A1

公开(公告)日：2009-04-30

申请号：PCT/US2008/075342

申请日：2008-09-05

Applicant: RAMBUS INC. ,  CHANG, Kun Yung ,  PEREGO, Richard E. ,  ASSADERAGHI, Fariborz

Inventor： CHANG, Kun Yung ,  PEREGO, Richard E. ,  ASSADERAGHI, Fariborz

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover, the stored mode setting may be dynamically configured (e.g., reprogrammed) during operation of the interface circuit so that subsequent digital signals are subsequently handled in accordance with a new mode setting.

Abstract translation: 描述装置的实施例。 该装置中的接口电路在总线上接收或发送数字信号，并且被配置为根据存储在寄存器中的模式设置交替地操作数据总线接口电路或控制总线接口电路。 例如，接口电路可以被预先配置为根据存储的模式设置将外部总线的线路解释为数据线或控制线。 此外，存储模式设置可以在接口电路的操作期间被动态配置（例如，重新编程），使得随后的数字信号随后根据新的模式设置进行处理。

公开(公告)号：WO2009048707A1

公开(公告)日：2009-04-16

申请号：PCT/US2008/075782

申请日：2008-09-10

Applicant: RAMBUS INC. ,  WOO, Steven C. ,  TSANG, Brian Hing-Kit ,  NG, William N. ,  SHAEFFER, Ian

Inventor： WOO, Steven C. ,  TSANG, Brian Hing-Kit ,  NG, William N. ,  SHAEFFER, Ian

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/08 ,  G06F12/1027 ,  G06F2212/2022 ,  G06F2212/205

Abstract: Embodiments of a circuit are described. This circuit includes an instruction fetch unit to fetch instructions to be executed which are associated with one or more virtual addresses, a translation lookaside buffer (TLB), and an execution unit to execute the instructions. Moreover, the TLB converts virtual addresses into physical addresses. Note that the TLB includes entries for physical addresses that are dedicated to dynamic random access memory (DRAM) and entries for physical addresses that are dedicated to a memory having a storage cell with a retention time that decreases as operations are performed on the storage cell.

Abstract translation: 描述电路的实施例。 该电路包括提取单元以提取与一个或多个虚拟地址相关联的要执行的指令，翻译后备缓冲器（TLB）以及执行指令的执行单元。 此外，TLB将虚拟地址转换为物理地址。 注意，TLB包括专用于动态随机存取存储器（DRAM）的物理地址条目和专用于具有存储单元的存储器的物理地址条目，存储单元具有随着对存储单元执行操作而减少的保留时间。

公开(公告)号：WO2009003129A3

公开(公告)日：2009-04-16

申请号：PCT/US2008068409

申请日：2008-06-26

Applicant: RAMBUS INC ,  LEE HAE-CHANG ,  REN JIHONG ,  LEIBOWITZ BRIAN S ,  MADDEN CHRISTOPHER J ,  LIN QI ,  ZERBE JARED L

Inventor： LEE HAE-CHANG ,  REN JIHONG ,  LEIBOWITZ BRIAN S ,  MADDEN CHRISTOPHER J ,  LIN QI ,  ZERBE JARED L

IPC: H04L25/02 ,  H04L1/20 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L1/203 ,  H04L1/205 ,  H04L25/0224 ,  H04L25/0242 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/03012 ,  H04L25/03343

Abstract: A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.

Abstract translation: 通信系统支持在相应的发送和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。 一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。 接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。 另一实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。 误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析位误差以测量通道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。 在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。