公开(公告)号：WO2005050231A1

公开(公告)日：2005-06-02

申请号：PCT/JP2004/005664

申请日：2004-04-28

Applicant: 株式会社アドバンテスト ,  須田 昌克 ,  須藤 訓 ,  岡安 俊幸

Inventor： 須田 昌克 ,  須藤 訓 ,  岡安 俊幸

IPC: G01R31/3181

CPC classification number: G01R31/31922 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00026 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/00 ,  H04L7/0037 ,  H04L7/0041

Abstract: 　本発明に係るデータサンプリング装置は、第１遅延量でデータ信号を順次遅延させる複数段の第１可変遅延素子と、第１遅延量より大きい第２遅延量でストローブ信号を順次遅延させる複数段の第２可変遅延素子と、複数段の第１可変遅延素子によって遅延された複数のデータ信号を、同一段の第２可変遅延素子によって遅延されたストローブ信号によりサンプリングする複数のタイミングコンパレータとを備え、タイミングコンパレータは、ストローブ信号に基づいてデータ信号を寄生容量によりラッチして出力するダイナミックＤ−ＦＦ回路と、ストローブ信号を遅延させるバッファと、遅延されたストローブ信号に基づいて、ダイナミックＤ−ＦＦ回路が出力した出力信号を、正帰還回路によりラッチして出力する正帰還Ｄ−ＦＦ回路とを有する。

Abstract translation: 数据采样装置包括：多级的第一可变延迟元件，用于以第一延迟量连续地延迟数据信号; 多级的第二可变延迟元件，用于以大于所述第一延迟量的第二延迟量连续延迟选通信号; 以及多个定时比较器，用于通过由相同级的第二可变延迟元件延迟的选通信号对由多级的第一可变延迟元件延迟的数据信号进行采样。 每个定时比较器包括：动态D-FF电路，用于根据选通信号将寄生电容锁存在数据信号上并将其输出; 用于延迟选通信号的缓冲器; 以及正反馈D-FF电路，用于根据延迟的选通信号通过正反馈电路来锁存来自动态D-FF电路的输出信号并将其输出。

公开(公告)号：WO0190864A3

公开(公告)日：2003-01-03

申请号：PCT/RU0100202

申请日：2001-05-22

Applicant: ABROSIMOV IGOR ANATOLIEVICH

Inventor： ABROSIMOV IGOR ANATOLIEVICH ,  DEAS ALEXANDER ROGER

IPC: H04L25/02 ,  G06F1/04 ,  G06F1/10 ,  G11C7/10 ,  G11C7/22 ,  H03L7/081 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/14

CPC classification number: H04L7/02 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L25/14

Abstract: The present invention relates to the reducing timing uncertainties in high-performance digital circuitry and more specifically, to a timing control means and a method for minimizing timing uncertainties due to skew and jitter. A means for the compensation of timing errors in multiple channel electronic devices comprising at least one register having a plurality of channels comprises: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers; wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's timing, the feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence and a set of delay means which uses the detected values of probability to generate a feedback signal. The invention is preferably implemented in a self calibrated receiver and a self calibrating transmitter. Also, the invention can be employed in a digital interface between two items or within a circuit where there is a requirement for tight timing control such as requirement for a low skew between the channels of a register.

Abstract translation: 本发明涉及高性能数字电路中的降低时序不确定性，更具体地，涉及一种定时控制装置和用于最小化由于偏斜和抖动引起的定时不确定性的方法。 用于补偿包括至少一个具有多个信道的寄存器的多信道电子设备中的定时误差的装置包括：用于提供时钟信号的时钟; 参考信号发生器，用于产生用于对所述寄存器进行偏移校正的参考信号; 其中对于每个所述寄存器，相应的反馈回路与寄存器定时的相对对准相关联，所述反馈回路包括用于检测由所述寄存器读取预定概率水平的偏差的装置，在两个参考通道的边界上的期望符号 序列中的符号和使用所检测的概率值产生反馈信号的一组延迟装置。 本发明优选地在自校准接收机和自校准发射机中实现。 此外，本发明可以用在两个项目之间的数字接口中，或者在需要紧密定时控制的电路中，例如对寄存器的通道之间的低偏移的要求。

公开(公告)号：WO2002091582A1

公开(公告)日：2002-11-14

申请号：PCT/US2002/014030

申请日：2002-05-03

Applicant: COREOPTICS, INC.

Inventor： REINHOLD, Mario ,  ROSE, Eduard ,  KUNZ, Frank

IPC: H03M1/12

CPC classification number: H04L7/007 ,  H03L7/00 ,  H03L7/06 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0337

Abstract: A circuit for generating a digital data signal from an analog input data signal is disclosed. The circuit comprises a master-slave flip-flop (70) with a clock input for receiving the analog input data signal, an amplitude detecting circuit (72) for detecting the amplitude of the analog input data signal and generating an amplitude detection signal (78) in response thereto, and a phase shifting circuit (84) responsive to the amplitude detection signal for supplying a phase shifted signal (90) to the clock input of the master-slave flip-flop. The circuit may further include a clock recovery circuit (92) for generating a recovered clock signal (96) from a clock signal contained in the analog input data signal. The recovered clock signal may be supplied to the amplitude detecting circuit, or a feedback loop may supply the phase shifted clock signal (100) to the amplitude detecting circuit.

Abstract translation: 公开了一种用于从模拟输入数据信号产生数字数据信号的电路。 电路包括具有用于接收模拟输入数据信号的时钟输入的主从触发器（70），用于检测模拟输入数据信号的振幅并产生振幅检测信号（78）的振幅检测电路（72） ）和响应于振幅检测信号的相移电路（84），用于向主从触发器的时钟输入提供相移信号（90）。 电路还可以包括用于根据包含在模拟输入数据信号中的时钟信号产生恢复的时钟信号（96）的时钟恢复电路（92）。 恢复的时钟信号可以被提供给振幅检测电路，或者反馈回路可以将相移时钟信号（100）提供给振幅检测电路。

公开(公告)号：WO2002078228A2

公开(公告)日：2002-10-03

申请号：PCT/RU2002/000120

申请日：2002-03-26

Applicant: ABROSIMOV, Igor Anatolievich

Inventor： ABROSIMOV, Igor Anatolievich ,  DEAS, Alexander, Roger

IPC: H04J3/00

CPC classification number: H04L7/0054 ,  H04L7/0037 ,  H04L7/0041 ,  H04L7/0045 ,  H04L7/033 ,  H04L25/14

Abstract: The present invention relates to the reduction of timing uncertainty in high speed communications channel or interface and to a receiver and method using the same. The receiver according to the invention comprises a plurality of samplers for latching data. The invention provides improvements to the Bit Error rate versus channel and inherent register noise, as a result of employment of the characteristic of phase noise within the receiving registers to measure the characteristics of the channel and to compensate for variations in the channel by altering the timing characteristics of the signal.

Abstract translation: 本发明涉及在高速通信信道或接口中不确定地减少时序。 根据本发明的接收机包括用于锁存数据的多个采样器。 本发明通过使用接收寄存器内的相位噪声的特性来测量信道的特性并且通过改变定时来补偿信道的变化，从而提供了比特误码率对信道和固有寄存器噪声的改进 信号的特点。

公开(公告)号：WO01090864A2

公开(公告)日：2001-11-29

申请号：PCT/RU2001/000202

申请日：2001-05-22

IPC: H04L25/02 ,  G06F1/04 ,  G06F1/10 ,  G11C7/10 ,  G11C7/22 ,  H03L7/081 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/14

CPC classification number: H04L7/02 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L25/14

Abstract: The present invention relates to the reducing timing uncertainties in high-performance digital circuitry and more specifically, to a timing control means and a method for minimizing timing uncertainties due to skew and jitter. A means for the compensation of timing errors in multiple channel electronic devices comprising at least one register having a plurality of channels comprises: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers; wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's timing, the feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence and a set of delay means which uses the detected values of probability to generate a feedback signal. The invention is preferably implemented in a self calibrated receiver and a self calibrating transmitter. Also, the invention can be employed in a digital interface between two items or within a circuit where there is a requirement for tight timing control such as requirement for a low skew between the channels of a register.

Abstract translation: 本发明涉及高性能数字电路中的降低时序不确定性，更具体地，涉及一种定时控制装置和用于最小化由于偏斜和抖动引起的定时不确定性的方法。 用于补偿包括至少一个具有多个信道的寄存器的多信道电子设备中的定时误差的装置包括：用于提供时钟信号的时钟; 参考信号发生器，用于产生用于对所述寄存器进行偏移校正的参考信号; 其中对于每个所述寄存器，相应的反馈回路与寄存器定时的相对对准相关联，所述反馈回路包括用于检测来自所述寄存器的预定读数概率的偏差的装置，在两个参考通道的边界上的期望符号 序列中的符号和使用所检测的概率值产生反馈信号的一组延迟装置。 本发明优选地在自校准接收机和自校准发射机中实现。 此外，本发明可以用于两个项目之间的数字接口中，或者在需要紧密定时控制的电路中，例如对寄存器的通道之间的低偏差的要求。

公开(公告)号：WO01048919A1

公开(公告)日：2001-07-05

申请号：PCT/IL2000/000868

申请日：2000-12-28

IPC: G11C27/02 ,  H03K5/00 ,  H03K5/13 ,  H03K5/156 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H03H11/26

CPC classification number: G11C27/02 ,  H03K5/131 ,  H03K5/133 ,  H03K5/1565 ,  H03K2005/00058 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/042 ,  H04L7/10

Abstract: Apparatus (28) for applying a delay to an input signal (50) includes a plurality of delay devices (40), each having an input and an output, coupled in series such that the output of each of the delay devices, except for a final delay device (51) in the series, is coupled to the input of a succeeding one of the delay devices in the series. A switching unit (34) is adapted to receive a delay selection signal indicative of a desired time delay and, responsive thereto, to couple the input signal to the input of a designated one of the delay devices, so as to generate an output signal (100) at the output of the final delay device which is delayed with respect to the input signal by the desired time delay.

Abstract translation: 用于向输入信号（50）施加延迟的装置（28）包括多个延迟装置（40），每个延迟装置具有串联耦合的输入和输出，使得每个延迟装置的输出除了 该系列中的最终延迟装置（51）被耦合到该系列中的后续的一个延迟装置的输入端。 切换单元（34）适于接收指示所需时间延迟的延迟选择信号，并且响应于此，将输入信号耦合到指定的一个延迟装置的输入端，以便产生输出信号（ 100）在相对于输入信号延迟所需时间延迟的最终延迟装置的输出端。

公开(公告)号：WO00031914A2

公开(公告)日：2000-06-02

申请号：PCT/DK1999/000648

申请日：1999-11-23

IPC: H03L7/081 ,  H03L7/087 ,  H03L7/089 ,  H04L7/027 ,  H04L7/033 ,  H04L7/00

CPC classification number: H03L7/0891 ,  H03L7/0812 ,  H03L7/087 ,  H04L7/0037 ,  H04L7/027 ,  H04L7/033

Abstract: By application of a method for recovering a digital data signal (Dout) and a clock signal (Ckout) from a received data signal (Din) consisting of a number of successive bits, a clock signal is produced from the received data signal by means of a resonator circuit (5). The recovered data signal is produced by sampling the received data signal with the recovered clock signal. The received data signal and the recovered clock signal are phase locked to each other so that the received data signal is sampled approximately in the centre of every bit. By phase locking the two signals to each other immediately prior to the sampling, the effect of varying time delays to which the two signals have been subjected individually on their way through the circuit is neutralised, and every sampling may be performed precisely within the very short time during which the data signal is stable.

Abstract translation: 通过应用从由多个连续位组成的接收数据信号（Din）中恢复数字数据信号（Dout）和时钟信号（Ckout）的方法，通过以下方式从接收数据信号产生时钟信号： 谐振器电路（5）。 恢复的数据信号通过用恢复的时钟信号对接收的数据信号进行采样而产生。 所接收的数据信号和恢复的时钟信号彼此相位锁定，使得接收的数据信号大约在每一位的中心被采样。 通过在采样之前立即将两个信号相互锁定在一起，两个信号在其通过电路的途中已经单独经受的变化的时间延迟的影响被中和，并且每个采样可以在非常短的时间内精确地执行 数据信号稳定的时间。

公开(公告)号：WO0011830A2

公开(公告)日：2000-03-02

申请号：PCT/US9919414

申请日：1999-08-25

Applicant: VITESSE SEMICONDUCTOR CORP

Inventor： MCCORMACK GARY D ,  TALAGA RONALD F JR ,  KYLES IAN A ,  MCCAMANT ANGUS J

IPC: H04L25/40 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/06

CPC classification number: H04L25/063 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0334

Abstract: A microprocessor (45) controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel (47a) and a monitor channel (47b). The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel are used to adjust the sampling and comparing of the signal in the data channel. The data recovery unit includes a PLL (35) based clock recovery unit in one embodiment, and in another embodiment the clock signal is derived by the microprocessor.

Abstract translation: 微处理器（45）控制数据恢复单元具有可调取样和信号比较级别。 数据恢复单元包括数据通道（47a）和监视通道（47b）。 监视器通道以不同的方式对输入的数据流进行采样。 监视通道中采样的结果用于调整数据通道中信号的采样和比较。 在一个实施例中，数据恢复单元包括基于PLL（35）的时钟恢复单元，在另一实施例中，时钟信号由微处理器导出。

公开(公告)号：WO1997031443A1

公开(公告)日：1997-08-28

申请号：PCT/GB1997000429

申请日：1997-02-14

Applicant: BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY ,  SMITH, Kevin ,  LUCEK, Julian, Kazimierz ,  PITCHER, Danny, Robert ,  WIDDOWSON, Terence ,  MOODIE, David, Graham

Inventor： BRITISH TELECOMMUNICATIONS PUBLIC LIMITED COMPANY

IPC: H04J14/08

CPC classification number: H04B10/505 ,  H04B10/508 ,  H04J14/08 ,  H04J14/083 ,  H04L7/0037 ,  H04L7/0075 ,  H04L7/0337

Abstract: A receiver at a node in an optical network receives an optical clock signal and a OTDM datastream. A detector converts the clock signal to the electrical domain. A variable delay stage applies a selected delay to the clock signal in the electrical domain. A non-linear electro-optic modulator which may be an electro-absorption modulator, receives the OTDM datastream at its optical input. An electrical control input of the modulator is connected to the output of the variable delay stage. The electro-optic modulator outputs an OTDM channel selected by setting the delay of the variable delay stage. The variable delay stage may comprise a number of logic gates, particularly AND gates, connected between a pair of microstrip delay lines. The gates are controlled to provide different paths with different corresponding delay times for the clock signal.

Abstract translation: 在光网络中的节点处的接收机接收光时钟信号和OTDM数据流。 检测器将时钟信号转换为电域。 可变延迟级将选择的延迟施加到电域中的时钟信号。 可以是电吸收调制器的非线性电光调制器在其光输入处接收OTDM数据流。 调制器的电气控制输入连接到可变延迟级的输出端。 电光调制器输出通过设置可变延迟级的延迟来选择的OTDM信道。 可变延迟级可以包括连接在一对微带延迟线之间的多个逻辑门，特别是与门。 控制门以为时钟信号提供具有不同相应延迟时间的不同路径。

公开(公告)号：WO1997025796A1

公开(公告)日：1997-07-17

申请号：PCT/US1996019622

申请日：1996-12-10

Applicant: CREDENCE SYSTEMS CORPORATION

Inventor： CREDENCE SYSTEMS CORPORATION ,  BEDELL, Daniel, J. ,  MILLER, Charles, A.

IPC: H04L07/00

CPC classification number: H04L7/0337 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041

Abstract: A system (10) for distributing synchronized clock signals to spatially distributed circuits (15) includes a pair of transmission lines (16, 18) between first (14) and second (24) sites. Deskewing circuits tap the signal transmission lines between the first and second sites. A first delay circuit (DELAY) in each deskewing circuit detects the outgoing clock signal on the first line and produceds a local clock signal (CLKL) that lags the outgoing clock signal by an adjustable delay. A similar second delay circuit in each deskewing circuit delays the local clock signal by a similar delay to produce a local reference signal. A phase lock controller (30) in each deskewing circuit adjusts the delay of the delay circuits so that the local reference signal is phase locked to the returning clock signal on the second line. When reference signals in all deskewing circuits are phase locked to the returning clock signal, their local clock signals have similar phases.

Abstract translation: 用于将同步时钟信号分配给空间分布电路（15）的系统（10）包括在第一（14）和第二（24）站点之间的一对传输线（16,18）。 倒塌电路分接第一和第二站点之间的信号传输线。 每个去歪斜电路中的第一延迟电路（DELAY）检测第一行上的输出时钟信号，并产生一个以可调延迟滞后于输出时钟信号的本地时钟信号（CLKL）。 每个去歪斜电路中的类似的第二延迟电路使本地时钟信号延迟相似的延迟以产生局部参考信号。 每个去歪斜电路中的锁相控制器（30）调节延迟电路的延迟，使得本地参考信号与第二行上的返回时钟信号锁相。 当所有的偏移电路中的参考信号被锁相到返回的时钟信号时，它们的本地时钟信号具有相似的相位。