公开(公告)号：WO2011163171A1

公开(公告)日：2011-12-29

申请号：PCT/US2011/041167

申请日：2011-06-21

Applicant: SUVOLTA, INC. ,  ARGHAVANI, Reza ,  SHIFREN, Lucian ,  RANADE, Pushkar ,  THOMPSON, Scott, E. ,  DE VILLENEUVE, Catherine

Inventor： ARGHAVANI, Reza ,  SHIFREN, Lucian ,  RANADE, Pushkar ,  THOMPSON, Scott, E. ,  DE VILLENEUVE, Catherine

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L27/0921 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/365 ,  H01L29/4966 ,  H01L29/66537 ,  H01L29/7836

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the V T setting within a precise range. This V T set range may be extended by appropriate selection of metals so that a very wide range of V T settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low oV T ) and VDD, so that the body bias can be tuned separately from V T for a given device.

Abstract translation: 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的sVT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置 更准确地说 指示特征性缺口的新型掺杂物分布使得能够在精确范围内调整VT设置。 可以通过适当选择金属来扩展该VT设定范围，使得在管芯上容纳非常宽范围的VT设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 结果是独立控制VT（具有低oVT）和VDD的能力，使得对于给定的器件，可以将体偏置与VT分开调谐。

公开(公告)号：WO2006026372A1

公开(公告)日：2006-03-09

申请号：PCT/US2005/030288

申请日：2005-08-25

Applicant: TESSERA, INC. ,  DE VILLENEUVE, Catherine ,  HUMPSTON, Giles ,  TUCKERMAN, David, B.

Inventor： DE VILLENEUVE, Catherine ,  HUMPSTON, Giles ,  TUCKERMAN, David, B.

IPC: H01L31/0203 ,  H01L31/0232 ,  H01L23/10 ,  H01L23/04

CPC classification number: H01L27/14618 ,  H01L23/04 ,  H01L23/10 ,  H01L27/14625 ,  H01L31/0203 ,  H01L31/02325 ,  H01L31/18 ,  H01L33/58 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01S5/02248 ,  H01S5/02292 ,  H01S5/4025 ,  H04N5/2257 ,  H01L2224/05599

Abstract: A covered chip (10 )having an optical element (14) integrated in the cover (12) is provided which includes a chip (11) having a front surface (18), an optically active circuit area (16), and bond pads (20) disposed at the front surface. The chip is covered by an at least partially optically translucent or transparent unitary cover (12) that is mounted to the front surface of the chip, and has at least one optical element (14) integrated in the unitary cover. The cover (12) is aligned with the optically active circuit area (16) and vertically spaced from the optically active circuit area.

Abstract translation: 提供一种具有集成在盖（12）中的光学元件（14）的覆盖芯片（10），其包括具有前表面（18），光学有效电路区域（16）和接合焊盘 20）设置在前表面。 该芯片由至少部分光学上半透明或透明的整体盖（12）覆盖，该盖（12）安装到芯片的前表面，并且具有集成在单一盖中的至少一个光学元件（14）。 盖（12）与光学有源电路区域（16）对准，并且与光学有源电路区域垂直间隔开。

公开(公告)号：WO2006026372A8

公开(公告)日：2007-03-29

申请号：PCT/US2005030288

申请日：2005-08-25

Applicant: TESSERA INC ,  DE VILLENEUVE CATHERINE ,  HUMPSTON GILES ,  TUCKERMAN DAVID B

Inventor： DE VILLENEUVE CATHERINE ,  HUMPSTON GILES ,  TUCKERMAN DAVID B

IPC: H01L31/0203 ,  H01L23/04 ,  H01L23/10 ,  H01L31/0232 ,  H01L31/18 ,  H03H9/10

CPC classification number: H01L27/14618 ,  H01L23/04 ,  H01L23/10 ,  H01L27/14625 ,  H01L31/0203 ,  H01L31/02325 ,  H01L31/18 ,  H01L33/58 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01S5/02248 ,  H01S5/02292 ,  H01S5/4025 ,  H04N5/2257 ,  H01L2224/05599

Abstract: A covered chip (10 ) having an optical element (14) integrated in the cover (12) is provided which includes a chip (11) having a front surface (18), an optically active circuit area (16), and bond pads (20) disposed at the front surface. The chip is covered by an at least partially optically translucent or transparent unitary cover (12) that is mounted to the front surface of the chip, and has at least one optical element (14) integrated in the unitary cover. The cover (12) is aligned with the optically active circuit area (16) and vertically spaced from the optically active circuit area.

Abstract translation: 提供一种具有集成在盖（12）中的光学元件（14）的覆盖芯片（10），其包括具有前表面（18），光学有效电路区域（16）和接合焊盘 20）设置在前表面。 该芯片由至少部分光学上半透明或透明的整体盖（12）覆盖，该盖（12）安装到芯片的前表面，并且具有集成在单一盖中的至少一个光学元件（14）。 盖（12）与光学有源电路区域（16）对准，并且与光学有源电路区域垂直间隔开。