LOW-STRESS VIAS
    1.
    发明申请
    LOW-STRESS VIAS 审中-公开
    低应力VIAS

    公开(公告)号:WO2013019541A4

    公开(公告)日:2013-05-30

    申请号:PCT/US2012048288

    申请日:2012-07-26

    Abstract: A component 10 can include a substrate 20 having a front surface 22 and a rear surface 21 remote therefrom, an opening 30 extending from the rear surface towards the front surface, and a conductive via 40 extending within the opening. The substrate 20 can have a CTE less than 10 ppm/°C. The opening 30 can define an inner surface 31 between the front and rear surfaces 22, 21. The conductive via 40 can include a first metal layer 41 overlying the inner surface 31 and a second metal region 42 overlying the first metal layer and electrically coupled to the first metal layer. The second metal region 42 can have a CTE greater than a CTE of the first metal layer 41. The conductive via 40 can have an effective CTE across a diameter D of the conductive via that is less than 80% of the CTE of the second metal region 42.

    Abstract translation: 部件10可以包括具有前表面22和远离其的后表面21的基板20,从后表面朝向前表面延伸的开口30以及在开口内延伸的导电通孔40。 基板20可以具有小于10ppm /℃的CTE。 开口30可以在前表面22和后表面21之间限定内表面31.导电通孔40可以包括覆盖在内表面31上的第一金属层41和覆盖第一金属层的第二金属区域42,并且电耦合到 第一个金属层。 第二金属区域42可以具有大于第一金属层41的CTE的CTE。导电通孔40可以具有穿过导电通孔的直径D的有效CTE,其小于第二金属的CTE的80% 区域42。

    LOW-STRESS VIAS
    2.
    发明申请
    LOW-STRESS VIAS 审中-公开
    低压力VIAS

    公开(公告)号:WO2013019541A3

    公开(公告)日:2013-04-18

    申请号:PCT/US2012048288

    申请日:2012-07-26

    Abstract: A component 10 can include a substrate 20 having a front surface 22 and a rear surface 21 remote therefrom, an opening 30 extending from the rear surface towards the front surface, and a conductive via 40 extending within the opening. The substrate 20 can have a CTE less than 10 ppm/°C. The opening 30 can define an inner surface 31 between the front and rear surfaces 22, 21. The conductive via 40 can include a first metal layer 41 overlying the inner surface 31 and a second metal region 42 overlying the first metal layer and electrically coupled to the first metal layer. The second metal region 42 can have a CTE greater than a CTE of the first metal layer 41. The conductive via 40 can have an effective CTE across a diameter D of the conductive via that is less than 80% of the CTE of the second metal region 42.

    Abstract translation: 部件10可以包括具有远离其的前表面22和后表面21的基板20,从后表面向前表面延伸的开口30以及在开口内延伸的导电通孔40。 衬底20可具有小于10ppm /℃的CTE。 开口30可以在前表面22和后表面21之间限定内表面31.导电通孔40可以包括覆盖内表面31的第一金属层41和覆盖第一金属层的第二金属区域42, 第一金属层。 第二金属区域42可以具有大于第一金属层41的CTE的CTE。导电通孔40可以在导电通孔的直径D上具有小于第二金属的CTE的80%的有效CTE 区域42。

    LOW-STRESS VIAS
    4.
    发明申请
    LOW-STRESS VIAS 审中-公开
    低压力VIAS

    公开(公告)号:WO2013019541A2

    公开(公告)日:2013-02-07

    申请号:PCT/US2012/048288

    申请日:2012-07-26

    Abstract: A component 10 can include a substrate 20 having a front surface 22 and a rear surface 21 remote therefrom, an opening 30 extending from the rear surface towards the front surface, and a conductive via 40 extending within the opening. The substrate 20 can have a CTE less than 10 ppm/°C. The opening 30 can define an inner surface 31 between the front and rear surfaces 22, 21. The conductive via 40 can include a first metal layer 41 overlying the inner surface 31 and a second metal region 42 overlying the first metal layer and electrically coupled to the first metal layer. The second metal region 42 can have a CTE greater than a CTE of the first metal layer 41. The conductive via 40 can have an effective CTE across a diameter D of the conductive via that is less than 80% of the CTE of the second metal region 42.

    Abstract translation: 组件10可以包括具有远离其的前表面22和后表面21的基板20,从后表面向前表面延伸的开口30以及在所述基板20内延伸的导电通路40。 开幕。 衬底20可以具有小于10ppm /℃的CTE。 开口30可以在前表面22和后表面21之间限定内表面31.导电通孔40可以包括覆盖内表面31的第一金属层41和覆盖第一金属层的第二金属区域42, 第一金属层。 第二金属区域42可以具有大于第一金属层41的CTE的CTE。导电通孔40可以在导电通孔的直径D上具有小于第二金属的CTE的80%的有效CTE 区域42。

    STACKED MICROELECTRONIC ASSEMBLY HAVING INTERPOSER CONNECTING ACTIVE CHIPS
    10.
    发明申请
    STACKED MICROELECTRONIC ASSEMBLY HAVING INTERPOSER CONNECTING ACTIVE CHIPS 审中-公开
    具有连接主动插座的插座的堆叠式微电子组件

    公开(公告)号:WO2012075371A1

    公开(公告)日:2012-06-07

    申请号:PCT/US2011/063025

    申请日:2011-12-02

    Abstract: A microelectronic assembly (100) can include first and second microelectronic elements (102, 112) each embodying active semiconductor devices adjacent a front surface (104, 114) thereof, and an interposer (120) of a material having a CTE less than 10 ppm/°C. Each microelectronic element (102, 112) can have a conductive pad (106, 116) exposed at the respective front surface (104, 114). The interposer (120) can have a second conductive element (118) extending within an opening (222) in the interposer and exposed at first and second surfaces (227, 229) of the interposer. The first and second surfaces (227, 229) can face the front surface (104, 114) of the respective first and second microelectronic elements (102, 112). Each microelectronic element (102, 112) can include a first conductive element (236, 238) extending within an opening (206, 216) extending from a rear surface (237, 239) towards the front surface (104, 114) of the respective microelectronic element. At least one of the first conductive elements (236, 238) can extend through the conductive pad (204, 214) of the respective first or second microelectronic element (102, 112).

    Abstract translation: 微电子组件(100)可以包括第一和第二微电子元件(102,112),每个微电子元件(102,112)各自体现邻近其前表面(104,114)的有源半导体器件,以及具有CTE小于10ppm的材料的插入件(120) /C。 每个微电子元件(102,112)可以具有在相应的前表面(104,114)处暴露的导电垫(106,116)。 插入器(120)可以具有在插入器中的开口(222)内延伸并在插入件的第一和第二表面(227,229)处露出的第二导电元件(118)。 第一和第二表面(227,229)可面对相应的第一和第二微电子元件(102,112)的前表面(104,114)。 每个微电子元件(102,112)可以包括第一导电元件(236,238),该第一导电元件(236,238)在从后表面(237,239)朝向相应的后表面(227,119)的前表面(104,114)延伸的开口(206,216)内延伸 微电子元件。 第一导电元件(236,238)中的至少一个可以延伸通过相应的第一或第二微电子元件(102,112)的导电焊盘(204,214)。

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