公开(公告)号：WO2011054009A8

公开(公告)日：2012-01-05

申请号：PCT/US2010055181

申请日：2010-11-02

Applicant: VISHAY SILICONIX ,  TERRILL KYLE

Inventor： TERRILL KYLE

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66696 ,  H01L21/743 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7836

Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.

Abstract translation: LDMOS（横向扩散的金属氧化物半导体）结构将源极连接到衬底以及栅极屏蔽，同时利用这种接触的减小的面积。 该结构包括导电基底层，源极和漏极接触; 漏极接触件通过至少一个中间层与基底层分离。 导电沟槽状馈通元件穿过中间层并接触衬底和源极以电连接漏极接触和衬底层。

公开(公告)号：WO2011163171A1

公开(公告)日：2011-12-29

申请号：PCT/US2011/041167

申请日：2011-06-21

Applicant: SUVOLTA, INC. ,  ARGHAVANI, Reza ,  SHIFREN, Lucian ,  RANADE, Pushkar ,  THOMPSON, Scott, E. ,  DE VILLENEUVE, Catherine

Inventor： ARGHAVANI, Reza ,  SHIFREN, Lucian ,  RANADE, Pushkar ,  THOMPSON, Scott, E. ,  DE VILLENEUVE, Catherine

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L27/0921 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/365 ,  H01L29/4966 ,  H01L29/66537 ,  H01L29/7836

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the V T setting within a precise range. This V T set range may be extended by appropriate selection of metals so that a very wide range of V T settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low oV T ) and VDD, so that the body bias can be tuned separately from V T for a given device.

Abstract translation: 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的sVT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置 更准确地说 指示特征性缺口的新型掺杂物分布使得能够在精确范围内调整VT设置。 可以通过适当选择金属来扩展该VT设定范围，使得在管芯上容纳非常宽范围的VT设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 结果是独立控制VT（具有低oVT）和VDD的能力，使得对于给定的器件，可以将体偏置与VT分开调谐。

公开(公告)号：WO2009086517A3

公开(公告)日：2009-10-08

申请号：PCT/US2008088439

申请日：2008-12-29

Applicant: VOLTERRA SEMICONDUCTOR CORP ,  ZUNIGA MARCO A ,  YOU BUDONG

Inventor： ZUNIGA MARCO A ,  YOU BUDONG

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/041 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7836

Abstract: A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.

Abstract translation: 晶体管包括源极，漏极和栅极。 源包括p-掺杂的p-体，与p-体重叠的p +区，与p +区邻近的p-体重叠的n +区，以及n掺杂源，重度双扩散（SHDD）区 仅进入晶体管的源极区域，SHDD区域的深度大约等于第一n +区域的深度并且与第一n +区域重叠。 漏极包括第二n +区域和与第二n +区域重叠的n掺杂浅漏极。 栅极在栅极氧化物上包括栅极氧化物和导电材料。 SHDD区域比栅氧化物下方的第一n +区域横向延伸更多。 使用比n掺杂的浅漏极的掺杂剂浓度大但比第一n +区域的掺杂剂浓度小的掺杂剂浓度来注入SHDD区域。

公开(公告)号：WO2009086517A2

公开(公告)日：2009-07-09

申请号：PCT/US2008/088439

申请日：2008-12-29

Applicant: VOLTERRA SEMICONDUCTOR CORPORATION ,  ZUNIGA, Marco, A. ,  YOU, Budong

Inventor： ZUNIGA, Marco, A. ,  YOU, Budong

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/26

CPC classification number: H01L21/041 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7836

Abstract: A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.

Abstract translation: 晶体管包括源极，漏极和栅极。 源包括p掺杂的p体，与p体重叠的p +区，与p +区相邻的p体重叠的n +区，以及n掺杂源，重双扩散（SHDD）区 仅在晶体管的源极区域中，SHDD区域的深度大约等于第一n +区域的深度并且与第一n +区域重叠。 漏极包括与第二n +区重叠的第二n +区和n掺杂的浅漏极。 栅极包括栅极氧化物和栅极氧化物上的导电材料。 SHDD区域比栅极氧化物下面的第一n +区域进一步横向延伸。 使用大于n掺杂浅漏极的掺杂浓度的掺杂浓度注入SHDD区，但是小于第一n +区的杂质浓度。

公开(公告)号：WO1991004577A1

公开(公告)日：1991-04-04

申请号：PCT/US1990005326

申请日：1990-09-19

Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM

Inventor： BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM ,  TASCH, Aloysious, Felix, Jr. ,  SHIN, Hyungsoon ,  MAZIAR, Christine, Marie

IPC: H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7836

Abstract: Hot-carrier suppression in a sub-micron MISFET structure is achieved by providing a drain region which includes a steeply profiled N+ (or P+) doped region in the surface of a semiconductor body with a first epitaxial layer formed thereover having N- (or P-) dopant concentration. A second N+ (or P+) epitaxial layer is formed over the first epitaxial layer and functions as a low ohmic contact to the drain region. In a preferred embodiment both the source and drain regions have dopant concentrations provided by N+ (or P+) doped regions in the surface of a substrate with epitaxial layers thereover. The dopant profile reduces the voltage drop across the more highly doped region of the drain and thereby reduces the electric field therein. Further, the reduction in dopant concentration reduces the electric field due to energy band bending associate with the change in doping level from the N+ (P+) region to the N- (P-) epitaxial layer. The resulting sub-micron device has better long-term reliability. The epitaxial layers are adjacent to and spaced from the gate contact by a dielectric layer such as silicon oxide. In a preferred embodiment, the dielectric layer is thicker between the second epitaxial layer and the gate contact than between the first epitaxial layer and the gate contact.

公开(公告)号：WO2012004053A1

公开(公告)日：2012-01-12

申请号：PCT/EP2011/058854

申请日：2011-05-30

Applicant: AUSTRIAMICROSYSTEMS AG ,  PARK, Jong Mun ,  RÖHRER, Georg

Inventor： PARK, Jong Mun ,  RÖHRER, Georg

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/4983 ,  H01L29/66484 ,  H01L29/66537 ,  H01L29/66568 ,  H01L29/7831 ,  H01L29/7836

Abstract: The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).

Abstract translation: 对称LDMOS晶体管包括半导体衬底（1），衬底中第一类导电性的阱（2）和与第二类导电性相反的阱（3）。 第二类导电性的孔（3）彼此间隔一定距离地布置。 源极/漏极区域（4）布置在第二导电类型的阱中。 栅极电介质（7）布置在衬底上，栅极电极（8）位于栅极电介质上。 第二类导电性的掺杂区域（10）被布置在第二导电类型的孔之间距离孔的距离处。 栅电极在掺杂区域（10）之上具有间隙（9），并且栅极重叠位于第二导电类型的阱（3）和掺杂区域（10）之间的区域。

公开(公告)号：WO2011054009A2

公开(公告)日：2011-05-05

申请号：PCT/US2010/055181

申请日：2010-11-02

Applicant: VISHAY-SILICONIX ,  TERRILL, Kyle

Inventor： TERRILL, Kyle

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66696 ,  H01L21/743 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7836

Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.

Abstract translation: LDMOS（横向扩散金属氧化物半导体）结构将源极连接到衬底以及栅极屏蔽，同时利用减小的面积用于这种接触。 该结构包括导电衬底层，源极和漏极触点; 漏极触点通过至少一个中间层与衬底层分离。 导电沟槽状馈通元件穿过中间层并接触衬底和源极以电连接漏极接触和衬底层。

公开(公告)号：WO2008079665A1

公开(公告)日：2008-07-03

申请号：PCT/US2007/087096

申请日：2007-12-12

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  MEHROTRA, Manoj ,  KIRMSE, Karen, Hildegard Ralston ,  SIDDIQUI, Shirin

Inventor： MEHROTRA, Manoj ,  KIRMSE, Karen, Hildegard Ralston ,  SIDDIQUI, Shirin

IPC: H01L21/8242

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

Abstract: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate (200). The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack (206) of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing suicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

Abstract translation: 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底（200）中的源极/漏极区。 然后移除宽的侧壁间隔物，并且在晶体管的栅极堆叠（206）旁边形成有细长的侧壁间隔物。 薄的间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的沟道，并且还通过允许形成更接近沟道的硅化物区域来有助于减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

公开(公告)号：WO2003088365A1

公开(公告)日：2003-10-23

申请号：PCT/JP2003/004814

申请日：2003-04-16

Applicant: 松下電器産業株式会社 ,  高木 剛

Inventor： 高木 剛

IPC: H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32105 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/7836 ,  H01L29/802

Abstract: 半導体基板１０上に、ゲート絶縁膜１１を介して下部ゲート電極膜を形成する工程と、下部ゲート電極膜上に、この下部ゲート電極膜よりも酸化速度の遅い材料からなる上部ゲート電極膜を形成する工程と、上部ゲート電極膜及び下部ゲート電極膜をパターニングして、下部ゲート電極１２ａ及び上部ゲート電極１２ｂを有するゲート電極１２を形成する工程と、半導体基板１０に不純物を導入してソース・ドレイン領域１５を形成する工程と、下部ゲート電極１２ａ及び上部ゲート電極１２ｂの側面を酸化し、下部ゲート電極１２ａの側方におけるゲート長方向の厚さが、上部ゲート電極１２ｂの側方におけるゲート長方向の厚さよりも大きい酸化膜サイドウォール１３を形成する工程とを備えている半導体装置の製造方法。　　　　　　　　　　　　　　　

Abstract translation: 一种半导体器件的制造方法，包括以下步骤：经由栅极绝缘膜（11）在半导体衬底（10）上形成下部栅极电极膜，形成上部栅极电极膜，所述上部栅极电极膜由比该缓冲层缓慢氧化的材料构成 下栅极电极膜，对上下栅电极膜进行构图以形成具有下栅极电极（12a）和上栅电极（12b）的栅极（12），将杂质引入到半导体衬底（10）中以形成 源极/漏极区域（15），并且氧化下部栅极电极（12a）的侧面和上部栅极电极（12b）的侧面以形成在栅极长度方向上较厚的氧化膜侧壁（13） （12a）的上侧栅电极（12b）侧的栅极长度方向的一侧。

公开(公告)号：WO1993009567A1

公开(公告)日：1993-05-13

申请号：PCT/US1992008291

申请日：1992-09-30

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  JOHNSON, Eric, A. ,  LOLF, Ying, T. ,  WANG, Chung, S.

IPC: H01L29/784

CPC classification number: H01L29/6659 ,  H01L21/28105 ,  H01L29/435 ,  H01L29/6656 ,  H01L29/7836

Abstract: In a method for producing an auxiliary gate lightly doped drain structure, a gate region (26) is placed on a substrate between two source/drain regions (21, 22). A first implant of atoms is made into the substrate on two sides of the gate region. Sidewalls (39, 49) are formed on the two sides of the gate region. Auxiliary gate regions (37, 47) are formed over the sidewalls. The auxiliary gate regions are separated from the gate region by the sidewalls. Dielectric regions (38, 48) are formed over the auxiliary gate regions. A second implant of atoms is performed into the substrate on two sides of the dielectric regions. The sidewalls and the auxiliary gate regions are composed of resistive material.

Abstract translation: 在用于制造辅助栅极轻掺杂漏极结构的方法中，栅极区域（26）被放置在两个源极/漏极区域（21,22）之间的衬底上。 原子的第一次注入在栅极区域的两侧被制成衬底。 侧壁（39,49）形成在栅极区域的两侧。 辅助栅极区域（37,47）形成在侧壁上。 辅助栅极区域通过侧壁与栅极区域分离。 电介质区域（38,48）形成在辅助栅极区域上。 在电介质区域的两侧进行第二次原子注入。 侧壁和辅助栅极区域由电阻材料构成。