公开(公告)号：WO2012145038A1

公开(公告)日：2012-10-26

申请号：PCT/US2012/000203

申请日：2012-04-17

Applicant: TELEDYNE RAD-ICON IMAGING CORP. ,  FARRIER, Michael, George ,  ROUMBANIS, John, Bernard

Inventor： FARRIER, Michael, George ,  ROUMBANIS, John, Bernard

IPC: H01L23/48

CPC classification number: H01L31/0232 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L27/14661 ,  H01L27/1469 ,  H01L31/186 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/4823 ,  H01L2224/4824 ,  H01L2224/49176 ,  H01L2224/75744 ,  H01L2224/83 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A method of making a tiled array of semiconductor dies includes aligning and flattening. One end of each semiconductor die has attached thereto a respective printed circuit board. The aligning aligns the semiconductor dies into the tiled array in such a way that the semiconductor dies rest on a vacuum plate and the one end of each die extends beyond an edge of the vacuum plate. The flattening flattens the semiconductor dies against the vacuum plate with a vacuum after the semiconductor dies are aligned.

Abstract translation: 制作半导体晶片的平铺阵列的方法包括对齐和平坦化。 每个半导体管芯的一端连接有相应的印刷电路板。 该对准将半导体管芯排列成平铺阵列，使得半导体管芯沉积在真空板上，并且每个管芯的一端延伸超过真空板的边缘。 在半导体管芯对准之后，扁平化使半导体管芯与真空板平齐。