DISCRETE BOOTSTRAPPING IN AN OPTICAL RECEIVER TO PREVENT SIGNAL FEEDBACK
    1.
    发明申请
    DISCRETE BOOTSTRAPPING IN AN OPTICAL RECEIVER TO PREVENT SIGNAL FEEDBACK 审中-公开
    光接收机中的隔离启动以防止信号反馈

    公开(公告)号:WO2007098433A3

    公开(公告)日:2008-05-15

    申请号:PCT/US2007062397

    申请日:2007-02-19

    Abstract: An optical receiver assembly that is configured to avoid the introduction of feedback in an electrical signal converted by the assembly is disclosed. In one embodiment, an optical receiver assembly is disclosed, comprising a capacitor, an optical detector provided with a power supply being mounted on a top electrode of the capacitor, and an amplifier mounted on the reference surface. The assembly further includes an isolator interposed between the reference surface and the capacitor, wherein the isolator includes a bottom layer of dielectric material that is affixed to a portion of the reference surface, and a metallic top plate that is electrically coupled both to a ground of the amplifier and to the capacitor. This configuration bootstraps the amplifier ground to the amplifier input via the photodiode top electrode of the capacitor to cancel out feedback signals present at the amplifier ground.

    Abstract translation: 公开了一种被配置为避免在由组件转换的电信号中引入反馈的光接收器组件。 在一个实施例中,公开了一种光接收器组件,包括电容器,设置有安装在电容器的顶部电极上的电源的光学检测器和安装在参考表面上的放大器。 组件还包括插入在参考表面和电容器之间的隔离器,其中隔离器包括固定到参考表面的一部分的介电材料的底层,以及金属顶板,其电耦合到 放大器和电容器。 该配置通过电容器的光电二极管顶部电极将放大器接地引导到放大器输入,以消除放大器地面上存在的反馈信号。

    DISTRIBUTED CLOCK TREE SCHEME IN SEMICONDUCTOR PACKAGES
    4.
    发明申请
    DISTRIBUTED CLOCK TREE SCHEME IN SEMICONDUCTOR PACKAGES 审中-公开
    分布式时钟树方案在半导体封装

    公开(公告)号:WO1993004500A1

    公开(公告)日:1993-03-04

    申请号:PCT/US1992005501

    申请日:1992-06-30

    Abstract: A clock plane (80) is embedded in the housing of a semiconductor chip package (14) where the plane (80) is connected to two or more clock pads (54, 56) on the semiconductor die (52) through vias, bonding fingers (62, 64) and bonding wires (72, 74). The two or more clock pads (54, 56) are connected by one or more clock lines (58). The clock plane (80) is connected by means of a via (112) to a clock input pin (116). In this manner, a clock signal fed to the clock input pin (116) is driven through the one or more clock line (58) with its tributaries from two separate locations by two or more input clock pads (54, 56). This reduces clock skew and permits a smaller area of the die surface (52) to be taken up by the clock lines.

    Abstract translation: 时钟平面嵌入在半导体芯片封装的壳体中,其中该平面通过通孔,接合指状物和接合线连接到半导体管芯上的两个或更多个时钟焊盘。 两个或更多个时钟垫由一个或多个时钟线连接。 时钟平面通过通孔连接到时钟iput引脚。 以这种方式,馈送到时钟输入引脚的时钟信号通过两个或多个输入时钟焊盘从两个分开的位置通过其一个或多个时钟线驱动。 这减少了时钟偏移,并允许芯片表面的较小面积被时钟线占据。

    DIRECT ATTACH OPTICAL RECEIVER MODULE AND METHOD OF TESTING
    8.
    发明申请
    DIRECT ATTACH OPTICAL RECEIVER MODULE AND METHOD OF TESTING 审中-公开
    直接连接光接收器模块和测试方法

    公开(公告)号:WO2004038964A2

    公开(公告)日:2004-05-06

    申请号:PCT/CA2003/001614

    申请日:2003-10-24

    Abstract: Optical receiver modules are used for receiving high-speed optical data signals. Unfortunately, these optical receiver modules are often tested for the first time after they are packaged in a housing. Thus significant costs are associated with those packaged devices that fail to meet predetermined criteria. An integrated optical receiver module is proposed that has an optical detector direct attached, or flip-chipped or bumped, onto an integrated circuit having an amplifier circuit. The direct attach process is performed when the integrated circuits still reside on a semiconductor wafer prior to dicing thereof. Thus, high speed optical testing of the optical receiver module is possible on a wafer level to determine actual performance characteristics thereof prior to dicing.

    Abstract translation: 光接收模块用于接收高速光数据信号。 不幸的是,这些光接收器模块在被封装在壳体中之后经常被首次测试。 因此,显着的成本与那些不符合预定标准的封装设备有关。 提出了一种集成光接收器模块,其具有直接附接或倒装或凸起到具有放大器电路的集成电路上的光学检测器。 当集成电路在其切割之前仍然驻留在半导体晶片上时,执行直接附接处理。 因此,可以在晶片级上对光接收器模块进行高速光学测试,以便在切割之前确定其实际的性能特征。

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