公开(公告)号：WO2006039028A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/030771

申请日：2005-08-30

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  CHEN, Jian ,  FILIPIAK, Stanley, M. ,  JEON, Yongjoo ,  STEPHENS, Tab, A.

Inventor： CHEN, Jian ,  FILIPIAK, Stanley, M. ,  JEON, Yongjoo ,  STEPHENS, Tab, A.

IPC: H01L21/4763 ,  H01L29/40

CPC classification number: H01L21/76832 ,  H01L21/743 ,  H01L21/76834 ,  H01L21/76897

Abstract: An etch stop (203) layer located over a plasma enhanced nitride (PEN) layer (132). Interlayer dielectric material is then formed over the etched stop layer. The etch stop layer is used as an etch stop for etching openings in the interlayer dielectric. In some embodiments, integrated circuits built with the PEN layer may include transistors with improved drive current at a given leakage current. Also, integrated circuits with the PEN layer may exhibit reduced parasitic capacitance.

Abstract translation: 位于等离子体增强氮化物（PEN）层（132）上方的蚀刻停止层（203）。 然后在蚀刻的停止层上形成层间电介质材料。 蚀刻停止层用作用于蚀刻层间电介质中的开口的蚀刻停止层。 在一些实施例中，用PEN层构建的集成电路可以包括在给定泄漏电流下具有改善的驱动电流的晶体管。 此外，具有PEN层的集成电路可以表现出降低的寄生电容。

公开(公告)号：WO2006098820A3

公开(公告)日：2007-04-26

申请号：PCT/US2006003531

申请日：2006-02-01

Applicant: FREESCALE SEMICONDUCTOR INC ,  GARCIA SAM S ,  MICHAELSON LYNNE M ,  ACOSTA EDWARD ,  CHATTERJEE RITWIK ,  FILIPIAK STANLEY M ,  MATHEW VARUGHESE

Inventor： GARCIA SAM S ,  MICHAELSON LYNNE M ,  ACOSTA EDWARD ,  CHATTERJEE RITWIK ,  FILIPIAK STANLEY M ,  MATHEW VARUGHESE

IPC: H01L23/48 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76849 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76856

Abstract: A diffusion barrier stack is formed by forming a layer (30) comprising a metal over a conductor (26) that includes copper; and forming a first dielectric layer (32) over the layer (30), wherein the dielectric layer (32) is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer (32) prevents oxidation of the layer (30). In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer (30) and the second layer is a dielectric layer (32). The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor (26).

Abstract translation: 通过在包括铜的导体（26）上形成包括金属的层（30）形成扩散阻挡层叠体; 以及在所述层（30）上形成第一介电层（32），其中所述电介质层（32）的厚度单独地不能用作所述导体的扩散阻挡层，并且所述第一介电层（32）防止 层（30）的氧化。 在一个实施例中，扩散阻挡堆叠包括两层; 第一层是导电层（30），第二层是介电层（32）。 扩散阻挡层将导电体（26）的电迁移和铜扩散最小化。

公开(公告)号：WO2005082122A2

公开(公告)日：2005-09-09

申请号：PCT/US2005/000961

申请日：2005-01-12

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  GARZA, Cesar, M. ,  DARLINGTON, William, D. ,  FILIPIAK, Stanley, M. ,  VASEK, James, E.

Inventor： GARZA, Cesar, M. ,  DARLINGTON, William, D. ,  FILIPIAK, Stanley, M. ,  VASEK, James, E.

IPC: H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/0273 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/66477 ,  H01L29/78 ,  Y10S438/945 ,  Y10S438/947

Abstract: A semiconductor device (50) is made by patterning a conductive layer (16) for forming gates (60, 62, 64) of transistors (80, 82, 84). The process for forming the gates (60, 62, 64) has a step of patterning photoresist (54, 56, 58) the overlies the conductive layer (16). The patterned photoresist (54, 56, 58) is trimmed so that its width is reduced. Fluorine, preferably F 2 , is applied to the trimmed photoresist (54, 56, 58) to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist (54, 56, 58) as a mask, the conductive layer (16) is etched to form conductive features useful as gates (60, 62, 64). Transistors (80, 82, 84) are formed in which the conductive pillars are gates (60, 62, 64). Other halogens, especially chlorine, may be substituted for the fluorine.

Abstract translation: 通过图案化用于形成晶体管（80,82,84）的栅极（60,62,64）的导电层（16）来制造半导体器件（50）。 用于形成栅极（60,62,64）的工艺具有将导电层（16）覆盖的光刻胶（54,56,58）图案化的步骤。 修整图案化的光致抗蚀剂（54,56,58），使其宽度减小。 将氟，优选F2施加到修剪的光致抗蚀剂（54,56,58）以增加其硬度和对导电层的选择性。 使用经修整的和氟化的光致抗蚀剂（54,56,58）作为掩模，蚀刻导电层（16）以形成用作栅极（60,62,64）的导电特征。 形成晶体管（80,82,84），其中导电柱是门（60,62,64）。 其他卤素，特别是氯可以代替氟。

公开(公告)号：WO2008002710A1

公开(公告)日：2008-01-03

申请号：PCT/US2007/066122

申请日：2007-04-06

Applicant: FREESCALE SEMICONDUCTOR INC. ,  SPENCER, Gregory S. ,  FILIPIAK, Stanley M. ,  RAMANI, Narayanan C. ,  TURNER, Michael D.

Inventor： SPENCER, Gregory S. ,  FILIPIAK, Stanley M. ,  RAMANI, Narayanan C. ,  TURNER, Michael D.

IPC: H01L21/26 ,  H01L21/335 ,  H01L21/336

CPC classification number: H01L21/268 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

Abstract: A strained semiconductor layer (12) is achieved by an overlying stressed dielectric layer (34). The stress in the dielectric layer (34) is increased by a radiation anneal (36). The radiation anneal (36) can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously. The heat is intense, preferably 900-1400 degrees Celcius, but for a very short duration of less than 10 milliseconds; preferably about 1 millisecond or even shorter. The result of the radiation anneal (36) can also be used to activate the source/drain. Thus, this type of radiation anneal can result in a larger change in stress, activation of the source/drain, and still no expansion of the source/drain (26, 28).

Abstract translation: 应变半导体层（12）通过覆盖的应力介电层（34）实现。 电介质层（34）中的应力通过辐射退火（36）增加。 辐射退火（36）可以是通过使用激光束进行扫描或者同时向整个电介质层提供退火的闪光工具。 热量很强，最好是900-1400摄氏度，但持续时间不到10毫秒; 优选约1毫秒甚至更短。 辐射退火（36）的结果也可用于激活源极/漏极。 因此，这种类型的辐射退火可以导致应力的变化更大，源极/漏极的激活，并且仍然没有源极/漏极（26,28）的膨胀。

公开(公告)号：WO2005082122A3

公开(公告)日：2006-02-16

申请号：PCT/US2005000961

申请日：2005-01-12

Applicant: FREESCALE SEMICONDUCTOR INC ,  GARZA CESAR M ,  DARLINGTON WILLIAM D ,  FILIPIAK STANLEY M ,  VASEK JAMES E

Inventor： GARZA CESAR M ,  DARLINGTON WILLIAM D ,  FILIPIAK STANLEY M ,  VASEK JAMES E

IPC: H01L21/027 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/66477 ,  H01L29/78 ,  Y10S438/945 ,  Y10S438/947

Abstract: A semiconductor device (50) is made by patterning a conductive layer (16) for forming gates (60, 62, 64) of transistors (80, 82, 84). The process for forming the gates (60, 62, 64) has a step of patterning photoresist (54, 56, 58) the overlies the conductive layer (16). The patterned photoresist (54, 56, 58) is trimmed so that its width is reduced. Fluorine, preferably F

Abstract translation: 通过图案化用于形成晶体管（80,82,84）的栅极（60,62,64）的导电层（16）来制造半导体器件（50）。 用于形成栅极（60,62,64）的工艺具有将导电层（16）覆盖的光刻胶（54,56,58）图案化的步骤。 修整图案化的光致抗蚀剂（54,56,58），使其宽度减小。 氟，优选F

公开(公告)号：WO2006135548A3

公开(公告)日：2007-11-22

申请号：PCT/US2006020401

申请日：2006-05-25

Applicant: FREESCALE SEMICONDUCTOR INC ,  GRUDOWSKI PAUL A ,  FILIPIAK STANLEY M ,  JEON YONGJOO ,  WEINTRAUB CHAD E

Inventor： GRUDOWSKI PAUL A ,  FILIPIAK STANLEY M ,  JEON YONGJOO ,  WEINTRAUB CHAD E

IPC: H01L21/336

CPC classification number: H01L21/76834 ,  H01L21/31111

Abstract: A method for forming a semiconductor device (10) comprises providing a semiconductor substrate (12); forming a first stressor layer (46) over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer (46); forming a second stressor layer (52) over the surface of the semiconductor substrate and the first stressor layer; and selectively removing portions of the second stressor layer using an isotropic etch. In one embodiment, the isotropic etch is a wet etch that selectively removes the second stressor layer (52) without removing a significant amount of the first stressor layer (46) and also planarizing a boundary between the first stressor layer and the second stressor layer.

Abstract translation: 一种形成半导体器件（10）的方法包括提供半导体衬底（12）; 在所述半导体衬底的表面上形成第一应力层（46）; 选择性地去除第一应力层（46）的部分; 在半导体衬底和第一应力层的表面上形成第二应力层（52）; 并且使用各向同性蚀刻选择性地去除第二应力层的部分。 在一个实施例中，各向同性蚀刻是湿蚀刻，其可选择性地去除第二应力层（52），而不去除大量的第一应力层（46），并且还平面化第一应力层和第二应力层之间的边界。

公开(公告)号：WO2006135548A2

公开(公告)日：2006-12-21

申请号：PCT/US2006/020401

申请日：2006-05-25

Applicant: FREESCALE SEMICONDUCTOR ,  GRUDOWSKI, Paul, A. ,  FILIPIAK, Stanley, M. ,  JEON, Yongjoo ,  WEINTRAUB, Chad, E.

Inventor： GRUDOWSKI, Paul, A. ,  FILIPIAK, Stanley, M. ,  JEON, Yongjoo ,  WEINTRAUB, Chad, E.

IPC: H01L21/469

CPC classification number: H01L21/76834 ,  H01L21/31111

Abstract: A method for forming a semiconductor device (10) comprises providing a semiconductor substrate (12); forming a first stressor layer (46) over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer (46); forming a second stressor layer (52) over the surface of the semiconductor substrate and the first stressor layer; and selectively removing portions of the second stressor layer using an isotropic etch. In one embodiment, the isotropic etch is a wet etch that selectively removes the second stressor layer (52) without removing a significant amount of the first stressor layer (46) and also planarizing a boundary between the first stressor layer and the second stressor layer.

Abstract translation: 一种形成半导体器件（10）的方法包括提供半导体衬底（12）; 在所述半导体衬底的表面上形成第一应力层（46）; 选择性地去除第一应力层（46）的部分; 在半导体衬底和第一应力层的表面上形成第二应力层（52）; 并且使用各向同性蚀刻选择性地去除第二应力层的部分。 在一个实施例中，各向同性蚀刻是湿蚀刻，其在不去除大量的第一应力层（46）的情况下选择性地去除第二应力层（52），并且还平面化第一应力层和第二应力层之间的边界。

公开(公告)号：WO2006098820A2

公开(公告)日：2006-09-21

申请号：PCT/US2006/003531

申请日：2006-02-01

Applicant: FREESCALE SEMICONDUCTOR ,  GARCIA, Sam, S. ,  MICHAELSON, Lynne, M. ,  ACOSTA, Edward ,  CHATTERJEE, Ritwik ,  FILIPIAK, Stanley, M. ,  MATHEW, Varughese

Inventor： GARCIA, Sam, S. ,  MICHAELSON, Lynne, M. ,  ACOSTA, Edward ,  CHATTERJEE, Ritwik ,  FILIPIAK, Stanley, M. ,  MATHEW, Varughese

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76856

Abstract: A diffusion barrier stack is formed by forming a layer (30) comprising a metal over a conductor (26) that includes copper; and forming a first dielectric layer (32) over the layer (30), wherein the dielectric layer (32) is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer (32) prevents oxidation of the layer (30). In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer (30) and the second layer is a dielectric layer (32). The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor (26).

Abstract translation: 通过在包括铜的导体（26）上形成包括金属的层（30）形成扩散阻挡层叠体; 以及在所述层（30）上形成第一介电层（32），其中所述电介质层（32）的厚度单独地不能用作所述导体的扩散阻挡层，并且所述第一介电层（32）防止 层（30）的氧化。 在一个实施例中，扩散阻挡堆叠包括两层; 第一层是导电层（30），第二层是介电层（32）。 扩散阻挡层将导电体（26）的电迁移和铜扩散最小化。