公开(公告)号：WO2016154339A1

公开(公告)日：2016-09-29

申请号：PCT/US2016/023817

申请日：2016-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： ROMIG, Matthew, D. ,  STEPNIAK, Frank ,  GANDHI, Saumya

IPC: H01L51/00 ,  H01G9/04 ,  H01L29/94 ,  B82Y40/00

CPC classification number: H01L23/5223 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/14 ,  H01L28/60 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H05K1/113 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0187 ,  H05K2201/0215 ,  H05K2201/10734

Abstract: In described examples, an electronic system includes an electronic body (301) with terminal pads (310) and at least one capacitor embedded in the electronic body. The capacitor includes: an insulating and adhesive first polymeric film (302) covering the body surface except the terminal pads; a sheet (320) of high-density capacitive elements, the first capacitor terminal being a metal foil (321) attached to the first polymeric film (302), the second terminal being a conductive polymeric compound (324), and the insulator being a dielectric skin (323). Sheet (320) has sets of via-holes, including: a first set of holes reaching the metal foil (321), a second set of holes reaching the terminals (310), and a third set of holes reaching the conductive polymeric compound (324). An insulating second polymeric film (303) lines the sidewalls of the holes and planarizes the sheet surface. Metal fills the via-holes between the polymeric sidewalls and forms conductive traces and attachment pads on the system surface.

Abstract translation: 在所描述的示例中，电子系统包括具有端子焊盘（310）的电子主体（301）和嵌入电子主体中的至少一个电容器。 所述电容器包括：绝缘和粘合的第一聚合物膜（302），其覆盖除了所述端子焊盘之外的所述主体表面; 高密度电容元件的片材（320），所述第一电容器端子是附着到所述第一聚合物膜（302）的金属箔（321），所述第二端子是导电聚合物（324），所述绝缘体是 介电皮肤（323）。 片（320）具有一组通孔，包括：到达金属箔（321）的第一组孔，到达端子（310）的第二组孔，以及到达导电聚合物的第三组孔 324）。 绝缘的第二聚合物膜（303）对孔的侧壁进行排列并使片表面平坦化。 金属填充聚合物侧壁之间的通孔，并在系统表面上形成导电迹线和附着垫。

公开(公告)号：WO2016132830A1

公开(公告)日：2016-08-25

申请号：PCT/JP2016/052256

申请日：2016-01-27

Applicant: 住友精密工業株式会社

Inventor： 松元　俊二

IPC: H01L21/3205 ,  H01L21/683 ,  H01L21/768 ,  H01L23/14 ,  H01L23/522

CPC classification number: H01L21/02118 ,  H01L21/02282 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/3205 ,  H01L21/32056 ,  H01L21/32115 ,  H01L21/6715 ,  H01L21/768 ,  H01L21/76897

Abstract: 　この充填方法は、処理室（１１）内を減圧する工程と、ウェハ（１）の表面に充填材料（３）を接触させる工程と、充填材料のウェハと反対側の面（３ａ）の全面を加圧することにより、ウェハの微細空間（２）に充填材料を差圧充填する工程と、ウェハの全体にわたって充填材料を焼成する工程と、を備える。

Abstract translation: 该填充方法包括：用于减小处理室（11）内的压力的步骤; 使填充材料（3）与晶片（1）的表面接触的步骤; 通过对填充材料的整个表面（3a）施加压力，通过差压填充晶片的精细空间（2）的步骤，所述表面位于晶片的相反侧， 侧面 以及在整个晶片中烧制填充材料的步骤。

公开(公告)号：WO2006055346A2

公开(公告)日：2006-05-26

申请号：PCT/US2005/040463

申请日：2005-11-08

Applicant: AXCELIS TECHNOLOGIES, INC. ,  WALDFRIED, Carlo ,  ESCORCIA, Orlando ,  BERRY, Ivan

Inventor： WALDFRIED, Carlo ,  ESCORCIA, Orlando ,  BERRY, Ivan

CPC classification number: H01L21/76825 ,  C23C16/56 ,  H01L21/02107 ,  H01L21/02203 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/31695 ,  H01L21/76826

Abstract: Processes for sealing porous low k dielectric film generally comprises exposing the porous surface of the porous low k dielectric film to ultraviolet (UV) radiation at intensities, times, wavelengths and in an atmosphere effective to seal the porous dielectric surface by means of carbonization, oxidation, and/or film densification. The surface of the surface of the porous low k material is sealed to a depth less than or equal to about 20 nanometers, wherein the surface is substantially free of pores after the UV exposure.

Abstract translation: 用于密封多孔低k电介质膜的方法通常包括将多孔低k电介质膜的多孔表面暴露于强度，时间，波长和大气中的紫外（UV）辐射，其有效地通过碳化，氧化来密封多孔电介质表面 ，和/或膜致密化。 多孔低k材料的表面的表面被密封到小于或等于约20纳米的深度，其中在UV暴露后该表面基本上没有孔。

公开(公告)号：WO2005017617A1

公开(公告)日：2005-02-24

申请号：PCT/US2003/034347

申请日：2003-10-27

Applicant: HONEYWELL INTERNATIONAL INC ,  HUANG, Wei ,  KENNEDY, Joseph ,  KATSANES, Ronald

Inventor： HUANG, Wei ,  KENNEDY, Joseph ,  KATSANES, Ronald

IPC: G03C1/00

CPC classification number: H01L21/02118 ,  C04B26/12 ,  C04B2111/00482 ,  C08J7/02 ,  C08J2361/00 ,  C23F1/10 ,  C23F1/44 ,  C23F3/00 ,  C23F3/04 ,  H01L21/31051 ,  H01L21/312 ,  Y10T428/31942 ,  C04B2103/0093 ,  C04B2103/40

Abstract: A planarization composition is disclosed herein that comprises: a) a structural constituent; and b) a solvent system, wherein the solvent system is compatible with the structural constituent and lowers the lowers at least one of the intermolecular forces or surface forces components of the planarization composition. A film that includes this planarization composition is also disclosed. In addition, another planarization composition is disclosed herein that comprises: a) a cresol-based polymer compound; and b) a solvent system comprising at least one alcohol and at least one ether acetate-based solvent. A film that includes this planarization composition is also disclosed. A layered component is also disclosed herein that comprises: a) a substrate having a surface topography; and b) a planarization composition or a film such as those described herein, wherein the composition is coupled to the substrate. Methods of forming a planarization compositions are also disclosed herein that comprise: a) providing a structural constituent; b) providing a solvent system, wherein the solvent system is compatible with the structural constituent and lowers at least one of the intermolecular forces or surface forces components of the planarization composition; and c) blending the structural constituent and the solvent system to form a planarization composition. Methods of forming a film are also disclosed that comprise: a) providing a planarization composition such as those disclosed herein; and b) evaporating at least part of the solvent system to form a film.

Abstract translation: 本文公开了一种平面化组合物，其包括：a）结构成分; 和b）溶剂体系，其中所述溶剂体系与所述结构组分相容并降低所述平坦化组合物的至少一种分子间力或表面力组分。 还公开了包含该平坦化组合物的膜。 此外，本文公开了另外的平坦化组合物，其包括：a）甲酚基聚合物化合物; 和b）包含至少一种醇和至少一种乙酸乙烯酯类溶剂的溶剂体系。 还公开了包含该平坦化组合物的膜。 本文还公开了一种分层组件，其包括：a）具有表面形貌的衬底; 和b）平面化组合物或诸如本文所述的那些的膜，其中所述组合物与所述基材偶联。 本文还公开了形成平坦化组合物的方法，其包括：a）提供结构成分; b）提供溶剂体系，其中所述溶剂体系与所述结构组分相容并降低所述平坦化组合物的分子间力或表面力组分中的至少一种; 和c）将结构成分和溶剂体系混合以形成平坦化组合物。 还公开了形成膜的方法，其包括：a）提供诸如本文公开的那些的平坦化组合物; 和b）蒸发至少部分溶剂系统以形成膜。

公开(公告)号：WO99043026A1

公开(公告)日：1999-08-26

申请号：PCT/US1999/003751

申请日：1999-02-19

IPC: H01L21/302 ,  C23C16/56 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/02131 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/31612 ,  H01L21/31629 ,  H01L21/76837

Abstract: A method and an apparatus for depositing a dielectric layer to fill in a gap between adjacent metal lines. In preferred embodiments of the method, a first dielectric layer is deposited over the lines and subsequently etched using both chemical and physical etchback steps. After the etchback steps are completed, a second dielectric layer is deposited over the first dielectric layer to fill in the gap.

Abstract translation: 一种用于沉积介电层以填充相邻金属线之间的间隙的方法和装置。 在该方法的优选实施例中，第一电介质层沉积在线上并随后使用化学和物理回蚀步骤进行蚀刻。 在回蚀步骤完成之后，第二介电层沉积在第一介电层上以填充间隙。

公开(公告)号：WO1996037912A1

公开(公告)日：1996-11-28

申请号：PCT/US1996006375

申请日：1996-05-06

Applicant: WATKINS-JOHNSON COMPANY

Inventor： WATKINS-JOHNSON COMPANY ,  FRY, Howard, W. ,  LIGHTFOOT, Kurt, J.

IPC: H01L21/306

CPC classification number: B24B37/013 ,  H01L21/31051 ,  H01L22/26

Abstract: A first layer of a first material is formed on a surface of a semiconductor substrate over circuit features to a predetermined thickness. A trace layer of a second material is formed on the first layer. Then a second layer of material is formed on the trace layer. The second layer is then planarized. During planarization, the trace layer above the circuit features will be reached as the second layer is removed. Upon reaching the trace layer, planarization will terminate.

Abstract translation: 第一材料的第一层在半导体衬底的表面上形成超过电路特征至预定厚度。 在第一层上形成第二材料的迹线层。 然后在迹线层上形成第二层材料。 然后将第二层平坦化。 在平坦化期间，随着第二层被去除，电路特征之上的迹线层将达到。 到达轨迹层时，平面化将终止。

公开(公告)号：WO1991019317A1

公开(公告)日：1991-12-12

申请号：PCT/CA1991000177

申请日：1991-05-28

Applicant: MITEL CORPORATION ,  OUELLET, Luc

Inventor： MITEL CORPORATION

IPC: H01L21/312

CPC classification number: H01L21/02129 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/31695 ,  H01L21/76801 ,  H01L23/291 ,  H01L23/3171 ,  H01L2924/0002 ,  Y10S438/902 ,  H01L2924/00

Abstract: A method of applying spin-on glass (SOG) on a substrate over low-melting point, non-refractory materials such as aluminium (1a, 1b) is disclosed. In the method a layer of applied spin-on glass (4) is subjected to disconnection and outgassing of water and reaction by-products, and then capped with a protective dielectric layer resistant to moisture diffusion (5).

Abstract translation: 公开了一种在低熔点的基材上施加旋涂玻璃（SOG）的方法，非耐火材料如铝（1a，1b）。 在该方法中，一层施加的旋涂玻璃（4）经受水和反应副产物的断开和除气，然后用耐潮湿扩散的保护性介电层（5）封盖。

公开(公告)号：WO1991012630A1

公开(公告)日：1991-08-22

申请号：PCT/CA1991000041

申请日：1991-02-06

Applicant: MITEL CORPORATION ,  OUELLET, Luc

Inventor： MITEL CORPORATION

IPC: H01L21/316

CPC classification number: H01L21/02129 ,  H01L21/02282 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31058 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/316 ,  H01L21/76801 ,  H01L21/76819 ,  H01L23/296 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of applying a spin-on glass layer to a substrate is disclosed characterized in that the spin-on glass is applied as a plurality of contiguous thin layers that together form a composite layer. Each thin layer is cured prior to the application of the next layer at a temperature of at least about 300 °C, preferably 350 °C, for a time sufficient to permit catalyst connection and substantially eliminate volatile residual solvents contained therein. In this way cracking in organic SOGs can be substantially eliminated, and beneficial results can also be achieved with quasi-organic SOGs.

公开(公告)号：WO2017112396A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/064955

申请日：2016-12-05

Applicant: INVENSAS CORPORATION

Inventor： SHEN, Hong ,  WANG, Liang ,  GAO, Gullian

IPC: H01L21/48 ,  H01L21/18 ,  H01L27/108 ,  H01L21/822

CPC classification number: H01L24/94 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/1436

Abstract: Systems and methods for providing 3D wafer assembly with known-good- dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

Abstract translation: 提供了用于提供具有已知良好模具的3D晶片组件的系统和方法。 示例方法编译半导体晶片上的裸片的索引并移除有缺陷的裸片以向晶片提供全部可操作的裸片。 可以并行移除多个晶片上的有缺陷的裸片，并且在3D晶片组件中堆叠具有所有良好裸片的所得晶片。 在一个实施方式中，被移除的有缺陷的模具留下的空间可以至少部分地用操作模具或填充材料填充。 可以在晶圆到晶圆组装之前或之后更换有缺陷的管芯，以消除有缺陷的堆叠器件的生产，或者空间可能被留空。 底部器件晶片也可能将其有缺陷的裸片移除或更换，从而导致提供没有缺陷裸片的3D堆叠的晶片 - 晶片组装。

公开(公告)号：WO2015089951A1

公开(公告)日：2015-06-25

申请号：PCT/CN2014/074360

申请日：2014-03-31

Applicant: 北京大学

Inventor： 黄如 ,  樊捷闻 ,  黎明 ,  杨远程 ,  宣浩然 ,  吴汉明 ,  卜伟海

IPC: H01L21/336

CPC classification number: H01L21/02271 ,  H01L21/31051 ,  H01L21/31105 ,  H01L29/0847 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834

Abstract: 提供一种制备准绝缘体上硅（SOI）源漏场效应晶体管器件的方法，包括如下步骤：形成器件的有源区；形成器件的栅叠层结构；形成源漏延伸区的掺杂，并在栅叠层两侧形成第一层侧墙（9）；形成凹陷的源漏结构；形成准SOI源漏隔离层（14）；原位掺杂外延第二半导体材料源漏（15），并进行退火激活；若采用后栅工艺则去掉之前的假栅，重新进行高k金属栅的淀积；形成接触和金属互联（21）。所述方法能很好地与现有互补金属氧化物半导体（CMOS）工艺兼容，具有工艺简单、热预算较小的特点，相比传统的场效应晶体管，依据所述方法制备的准SOI源漏场效应晶体管器件能有效降低泄漏电流，减小器件的功耗。