公开(公告)号：WO2016204772A1

公开(公告)日：2016-12-22

申请号：PCT/US2015/036522

申请日：2015-06-18

Applicant: INTEL CORPORATION ,  ROMERO, Patricio E.

Inventor： ROMERO, Patricio E.

IPC: C07F1/02 ,  H01L21/205 ,  C23C16/44 ,  C23C16/455

CPC classification number: C07F1/005 ,  C23C16/04 ,  C23C16/18 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76897

Abstract: Inherently selective precursors for deposition of second or third row transition metal (e.g., tungsten or ruthenium) thin films are described. In an example, a ligand framework for second or third row transition metal complex formation includes a lithium complex.

Abstract translation: 描述了用于沉积第二或第三行过渡金属（例如钨或钌）薄膜的固有选择性前体。 在一个实例中，用于第二或第三行过渡金属络合物形成的配体框架包括锂络合物。

公开(公告)号：WO2015147843A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/032073

申请日：2014-03-27

Applicant: INTEL CORPORATION ,  BLACKWELL, James M. ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  KLOSTER, Grant M. ,  GSTREIN, Florian ,  SIMKA, Harsono S. ,  ZIMMERMAN, Paul A. ,  BRISTOL, Robert L.

Inventor： BLACKWELL, James M. ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  KLOSTER, Grant M. ,  GSTREIN, Florian ,  SIMKA, Harsono S. ,  ZIMMERMAN, Paul A. ,  BRISTOL, Robert L.

IPC: C23C16/455 ,  C23C16/52 ,  H01L21/285

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Abstract translation: 描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。 在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。 该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。

公开(公告)号：WO2015047345A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062456

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  BRISTOL, Robert L. ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  HAN, Eungnak ,  KLOSTER, Grant M. ,  ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  HOURANI, Rami

Inventor： BRISTOL, Robert L. ,  BLACKWELL, James M. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  HAN, Eungnak ,  KLOSTER, Grant M. ,  ROBERTS, Jeanette M. ,  ROMERO, Patricio E. ,  HOURANI, Rami

IPC: H01L21/31

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过分开地通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

公开(公告)号：WO2019066825A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/053843

申请日：2017-09-27

Applicant: INTEL CORPORATION ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  TAN, Cen

Inventor： ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  GSTREIN, Florian ,  TAN, Cen

IPC: H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.

公开(公告)号：WO2018009158A1

公开(公告)日：2018-01-11

申请号：PCT/US2016/040894

申请日：2016-07-02

Applicant: INTEL CORPORATION ,  CLENDENNING, Scott B. ,  KIM, Kyoung H. ,  ROMERO, Patricio E.

Inventor： CLENDENNING, Scott B. ,  KIM, Kyoung H. ,  ROMERO, Patricio E.

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/78

Abstract: An apparatus including an integrated circuit device structure including a metal layer including a composition of General Formula I: M-Al m -X 1 n -X 2 p -C q -O r , wherein M includes a metal selected from one or more of titanium, zirconium, hafnium, tantalum, niobium and vanadium, wherein C includes carbon, wherein X 1 includes gallium, wherein X 2 includes indium, wherein m, n, p, q and r represent an atomic percent of an element in the metal layer that can be 0 percent, with the proviso that n and p cannot each be 0 percent. A method including introducing a first precursor including a metal halide into a chamber including an integrated circuit structure, introducing a second precursor of at least one of an organogallium compound and organoindium compound into the chamber; and depositing a metal including the metal cation of the halide and at least one of gallium and indium.

Abstract translation: 一种包括集成电路器件结构的设备，所述集成电路器件结构包括包含通式I的组成的金属层：M-Al m -X 1 ^{1 其中M包括一个或多个取代基，其中M包括一个或一个以上的取代基， 选自钛，锆，铪，钽，铌和钒中的一种或多种的金属，其中C包括碳，其中X 1包括镓，其中X 2包括铟， 其中m，n，p，q和r表示金属层中元素的原子百分比，其可以为0％，条件是n和p不能各为0％。 包括将包含金属卤化物的第一前体引入包括集成电路结构的腔室中，将有机镓化合物和有机铟化合物中的至少一种的第二前体引入腔室中; 并沉积包括卤化物的金属阳离子和镓和铟中的至少一种的金属。}

公开(公告)号：WO2016204757A1

公开(公告)日：2016-12-22

申请号：PCT/US2015/036302

申请日：2015-06-17

Applicant: INTEL CORPORATION ,  ROMERO, Patricio, E. ,  PLOMBON, John, J.

Inventor： ROMERO, Patricio, E. ,  PLOMBON, John, J.

IPC: H01L21/3065

CPC classification number: H01L21/32135 ,  H01L21/28079 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Transition metal dry etch by atomic layer removal of oxide layers for device fabrication, and the resulting devices, are described. In an example, a method of etching a film includes reacting a surface layer of a transition metal species of a transition metal-containing film with a molecular oxidant species. The method also includes removing volatile fragments of the reacted molecular oxidant species to provide an oxidized surface layer of the transition metal species. The method also includes reacting the oxidized surface layer of the transition metal species with a molecular etchant. The method also includes removing the reacted oxidized surface layer of the transition metal species and the reacted molecular etchant by volatlilization.

Abstract translation: 描述了通过用于器件制造的氧化物层的原子层去除的过渡金属干法蚀刻以及所得到的器件。 在一个实例中，蚀刻膜的方法包括使含过渡金属的膜的过渡金属物质的表面层与分子氧化物物质反应。 该方法还包括除去反应的分子氧化剂物质的挥发性碎片以提供过渡金属物质的氧化表面层。 该方法还包括使过渡金属物质的氧化表面层与分子蚀刻剂反应。 该方法还包括通过挥发除去过渡金属物质的反应氧化表面层和反应的分子蚀刻剂。

公开(公告)号：WO2018118086A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068579

申请日：2016-12-23

Applicant: INTEL CORPORATION ,  ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  TAN, Cen

Inventor： ROMERO, Patricio E. ,  CLENDENNING, Scott B. ,  TAN, Cen

IPC: H01L21/02 ,  C07F19/00

Abstract: Gallium-based co-reactants for fabricating metal silicide and metal germanide films, and integrated circuit structures including such films, are described. In a first example, a discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a silicon-based moiety having a central silicon atom. The central silicon atom of the silicon-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. In a second example, a discrete acyclic molecule includes a gallium-based moiety having a central gallium atom, and a germanium-based moiety having a central germanium atom. The central germanium atom of the germanium-based moiety and the central gallium atom of the gallium-based moiety are covalently bonded to one another with a single bond. In either case, a neutral Lewis basic ligand is bonded to the central gallium atom of the gallium-based moiety.

公开(公告)号：WO2016048336A1

公开(公告)日：2016-03-31

申请号：PCT/US2014/057585

申请日：2014-09-26

Applicant: INTEL CORPORATION ,  CLENDENNING, Scott B. ,  LIAO, Szuya S. ,  GSTREIN, Florian ,  HOURANI, Rami ,  ROMERO, Patricio E. ,  KLOSTER, Grant M. ,  MITAN, Martin M.

Inventor： CLENDENNING, Scott B. ,  LIAO, Szuya S. ,  GSTREIN, Florian ,  HOURANI, Rami ,  ROMERO, Patricio E. ,  KLOSTER, Grant M. ,  MITAN, Martin M.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0673 ,  H01L21/265 ,  H01L21/28247 ,  H01L29/42364 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

Abstract translation: 讨论了与形成用于半导体器件和晶体管结构的选择性栅极间隔物以及使用这种技术形成的器件有关的技术。 这样的技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同的表面化学性质的栅极，在栅极上形成选择性共形层，而不是在阻挡材料的一部分上， 以及去除封闭材料的暴露部分。

公开(公告)号：WO2013147856A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031486

申请日：2012-03-30

Applicant: INTEL CORPORATION ,  ZIMMERMAN, Paul A. ,  CLENDENNING, Scott B. ,  ROMERO, Patricio E. ,  FISCHER, Paul B. ,  EDGEWORTH, Robert

Inventor： ZIMMERMAN, Paul A. ,  CLENDENNING, Scott B. ,  ROMERO, Patricio E. ,  FISCHER, Paul B. ,  EDGEWORTH, Robert

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/60 ,  H01L23/642 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

Abstract translation: 公开了形成实现负热膨胀（NTE）材料如钨酸锆（ZrW2O8）或钨酸铪（HfW2O8）的穿硅通孔（TSV）的技术。 在一些情况下，NTE材料设置在TSV的衬底和导电芯材之间，并且用于至少部分地抵消其间的热膨胀系数（CTE）失配，从而减少热诱导的应力和/或 突出（泵送）导电芯材料。 NTE材料还可以防止导电芯材料的泄漏，电压击穿和/或扩散。 此外，NTE材料可以降低高纵横比TSV中的径向应力。 在一些情况下，本文公开的技术可以提高三维集成电路和/或其他三维封装中的TSV可靠性，增强三维集成和/或增强性能。 根据本公开，可以使用本文描述的技术的其他实施例将是显而易见的。

公开(公告)号：WO2016099570A1

公开(公告)日：2016-06-23

申请号：PCT/US2014/071717

申请日：2014-12-19

Applicant: INTEL CORPORATION ,  KLOSTER, Grant ,  CLENDENNING, Scott B. ,  HOURANI, Rami ,  LIAO, Szuya S. ,  ROMERO, Patricio E. ,  GSTREIN, Florian

Inventor： KLOSTER, Grant ,  CLENDENNING, Scott B. ,  HOURANI, Rami ,  LIAO, Szuya S. ,  ROMERO, Patricio E. ,  GSTREIN, Florian

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

Abstract translation: 公开了在半导体结构上选择性地沉积高K栅极电介质的方法。 该方法包括提供设置在半导体衬底之上的半导体结构。 半导体结构设置在隔离侧壁旁边。 牺牲阻挡层然后选择性地沉积在隔离侧壁上，而不是半导体结构上。 此后，高K栅极电介质沉积在半导体结构上，但不沉积在牺牲阻挡层上。 牺牲阻挡层的性质防止氧化物材料在其表面上的沉积。 然后进行热处理以去除牺牲阻挡层，从而仅在半导体结构上形成高K栅极电介质。