Abstract:
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.
Abstract:
본 발명에 따른 건식 박리 방법은, 포토레지스트를 애싱하는 건식 박리 방법으로서, 상기 포토레지스트에 승화성 입자를 분사하여 상기 포토레지스트를 박리하는 분사및 박리 단계를 포함하는 것을 특징으로 한다. 그리고, 본 발명에 따른 건식 박리 장치는 포토레지스트를 애싱하는 건식 박리 장치로서, 승화성 입자로 이루어진 고속 입자 빔을 생성하는 노즐을 포함하되, 상기 노즐은, 이산화탄소로 이루어진 입자생성가스를 통과시켜 초고속 균일 나노 입자를 생성하는 노즐로서, 노즐의 출구측으로 갈수록 단면적이 넓어지는 형태의 팽창부를 포함하되, 상기 팽창부는 제1팽창부 및 제2팽창부를 순차적으로 포함하여 이루어지며, 상기 제2팽창부의 평균 팽창각이 상기 제1팽창부의 팽창각 보다 큰 것을 특징으로 한다.
Abstract:
Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber. The plasma etch chamber also includes a cathode assembly disposed below the plasma source. The cathode assembly includes a cooling RF-powered chuck for supporting an inner portion of a backside of a substrate carrier. The cathode assembly also includes a cooling RF-isolated support surrounding but isolated from the RF-powered chuck. The RF-isolated support is for supporting an outer portion of the backside of the substrate carrier.
Abstract:
Methods of using a hybrid mask composed of a first water soluble film layer and a second water-soluble layer for wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a hybrid mask above the semiconductor wafer. The hybrid mask is composed of a first water-soluble layer disposed on the integrated circuits, and a second water-soluble layer disposed on the first water-soluble layer. The method also involves patterning the hybrid mask with a laser scribing process to provide a patterned hybrid mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also involves etching the semiconductor wafer through the gaps in the patterned hybrid mask to singulate the integrated circuits.
Abstract:
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The patterned mask is then separated from the singulated integrated circuits.
Abstract:
Embodiments of the present invention provide methods for fabricating graphene nanoelectronic devices with semiconductor compatible processes, which allow wafer scale fabrication of graphene nanoelectronic devices. Embodiments of the present invention also provide methods for passivating graphene nanoelectronic devices, which enable stacking of multiple graphene devices and the creation of high density graphene based circuits. Other embodiments provide methods for producing devices with graphene layer segments having multiple thicknesses.
Abstract:
An imprint apparatus cures an imprint material supplied onto a substrate held by a substrate holder by bringing a mold held by a mold holder into contact with the imprint material. The imprint apparatus includes an adjuster to adjust a distance between the substrate holder and the mold holder for contact and separation between the imprint material and the mold, an energy supply tool to supply, to the imprint material, energy for curing the imprint material supplied onto the substrate held by the substrate holder, and a controller to control the adjuster and the energy supply tool. The controller controls the adjuster so as to start separation between the imprint material and the mold in a period during which the energy supply tool supplies the energy to the imprint material that is in contact with the mold.