公开(公告)号：WO2010065290A3

公开(公告)日：2010-08-19

申请号：PCT/US2009064813

申请日：2009-11-17

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  RICHARDSON WAYNE ,  KASAMSETTY KISHORE

Inventor： WARE FREDERICK A ,  RICHARDSON WAYNE ,  KASAMSETTY KISHORE

IPC: G06F13/32 ,  G06F11/10 ,  G06F12/00 ,  G06F13/24

CPC classification number: G11C29/56 ,  G01R31/3171 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50012 ,  G11C29/56012

Abstract: A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.

Abstract translation: 存储器系统包括经由高速数据和请求链路耦合到至少一个存储器设备的存储器控​​制器。 链路的定时和电压裕度被定期校准，以减少位误差。 高速请求链接使校准变得复杂，因为通过未校准的请求链接发出的命令可能被存储器件错误地解释。 错误解释的命令可能会中断校准过程（例如，写命令可能被误解为掉电命令）。 存储器控制器使用单独的低速控制接口来解决这个问题，发出一个过滤器命令，指示当处于校准模式时存储器件可能会破坏潜在的破坏性请求。

公开(公告)号：WO2006107709A1

公开(公告)日：2006-10-12

申请号：PCT/US2006/011688

申请日：2006-03-30

Applicant: RAMBUS INCORPORATED ,  KASAMSETTY, Kishore ,  LAI, Lawrence ,  RICHARDSON, Wayne

Inventor： KASAMSETTY, Kishore ,  LAI, Lawrence ,  RICHARDSON, Wayne

IPC: G11C7/10

CPC classification number: G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device comprises an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

Abstract translation: 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：WO2012154507A1

公开(公告)日：2012-11-15

申请号：PCT/US2012/036370

申请日：2012-05-03

Applicant: RAMBUS INC. ,  BANSAL, Akash ,  FRANS, Yohan U. ,  KASAMSETTY, Kishore V. ,  BYSTROM, Todd ,  LI, Simon ,  VAIDYANATH, Arun

Inventor： BANSAL, Akash ,  FRANS, Yohan U. ,  KASAMSETTY, Kishore V. ,  BYSTROM, Todd ,  LI, Simon ,  VAIDYANATH, Arun

IPC: G11C7/00 ,  G06F1/04

CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

Abstract translation: 公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中相应的数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2速率，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

公开(公告)号：WO2008014413A3

公开(公告)日：2008-01-31

申请号：PCT/US2007/074513

申请日：2007-07-26

Applicant: RAMBUS INC. ,  WARE, Frederick A. ,  KASAMSETTY, Kishore ,  LAI, Lawrence ,  FANG, Wayne ,  PENG, Liang

Inventor： WARE, Frederick A. ,  KASAMSETTY, Kishore ,  LAI, Lawrence ,  FANG, Wayne ,  PENG, Liang

IPC: G06F13/16

Abstract: Within an integrated-circuit (IC) memory device, and during a first interval, a first storage location within a first memory array and a second storage location within a second memory array are concurrently accessed via first and second external signaling interfaces, respectively. During a second interval, a third storage location within the first memory array and a fourth storage location within the second memory array are concurrently accessed via the first and second external signaling interfaces.

公开(公告)号：WO2010117535A2

公开(公告)日：2010-10-14

申请号：PCT/US2010/026757

申请日：2010-03-10

Applicant: RAMBUS INC. ,  WARE, Frederick A. ,  BROOKS, John Welsford ,  KASAMSETTY, Kishore Ven ,  PEREGO, Richard E.

Inventor： WARE, Frederick A. ,  BROOKS, John Welsford ,  KASAMSETTY, Kishore Ven ,  PEREGO, Richard E.

IPC: G06F13/16 ,  G06F12/02 ,  G06F9/30

CPC classification number: G06F13/161

Abstract: The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device.

Abstract translation: 本实施例提供了一种被配置为从存储器控制器向存储器件发送请求的存储器系统，其中该请求包括独立的激活和预充电命令。 activate命令与行地址相关联，该行地址标识了activate命令的第一行。 响应于激活命令，系统激活存储器设备中的第一组中的第一行。 类似地，响应于预充电命令，系统对存储器件中的第二存储体进行预充电。

公开(公告)号：WO2010017015A1

公开(公告)日：2010-02-11

申请号：PCT/US2009/051081

申请日：2009-07-17

Applicant: RAMBUS INC. ,  KASAMSETTY, Kishore, Ven ,  RICHARDSON, Wayne, S. ,  KNORPP, Kurt ,  WARE, Frederick, A.

Inventor： KASAMSETTY, Kishore, Ven ,  RICHARDSON, Wayne, S. ,  KNORPP, Kurt ,  WARE, Frederick, A.

IPC: G11C29/16 ,  G11C29/18

CPC classification number: G11C29/16 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/56012

Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.

Abstract translation: 描述存储器件的实施例。 该存储装置包括电连接到命令/地址（CA）链路的信号连接器和电耦合到信号连接器并且经由CA链路接收CA分组的接口电路。 给定的CA分组包括具有与存储设备中的一个或多个存储位置相对应的地址信息的地址字段。 此外，存储器件包括具有两种操作模式的控制逻辑，其中在第一操作模式期间，控制逻辑使用全场采样来解码CA分组中的地址信息，并且在第二操作模式期间，控制逻辑解码 CA分组中的部分地址信息使用子场采样。

公开(公告)号：WO2012115839A1

公开(公告)日：2012-08-30

申请号：PCT/US2012/025310

申请日：2012-02-15

Applicant: RAMBUS INC. ,  ELLIS, Wayne F. ,  RICHARDSON, Wayne S. ,  BANSAL, Akash ,  WARE, Frederick A. ,  LAI, Lawrence ,  KASAMSETTY, Kishore Ven

Inventor： ELLIS, Wayne F. ,  RICHARDSON, Wayne S. ,  BANSAL, Akash ,  WARE, Frederick A. ,  LAI, Lawrence ,  KASAMSETTY, Kishore Ven

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/402 ,  G06F13/14

CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract translation: 在一个实施例中，存储器设备包括存储器核心和用于接收命令和数据的输入接收器。 存储器装置还包括寄存器，用于存储指示输入接收器的子集是否响应于控制信号掉电的值。 存储器控制器将命令和数据发送到存储器件。 存储器控制器还发送该值以指示存储器件的输入接收器的子集是否响应于控制信号掉电。 此外，响应于自我新命令，存储装置延迟进入自刷新操作，直到接收到接收到自刷新命令之后接收到的控制信号。

公开(公告)号：WO2008014413A2

公开(公告)日：2008-01-31

申请号：PCT/US2007074513

申请日：2007-07-26

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  KASAMSETTY KISHORE ,  LAI LAWRENCE ,  FANG WAYNE ,  PENG LIANG

Inventor： WARE FREDERICK A ,  KASAMSETTY KISHORE ,  LAI LAWRENCE ,  FANG WAYNE ,  PENG LIANG

CPC classification number: G06F13/1684 ,  G06F13/1652

Abstract: Within an integrated-circuit (IC) memory device, and during a first interval, a first storage location within a first memory array and a second storage location within a second memory array are concurrently accessed via first and second external signaling interfaces, respectively. During a second interval, a third storage location within the first memory array and a fourth storage location within the second memory array are concurrently accessed via the first and second external signaling interfaces.

Abstract translation: 在集成电路（IC）存储器设备内，并且在第一间隔期间，第一存储器阵列内的第一存储位置和第二存储器阵列内的第二存储位置分别经由第一和第二外部信令接口同时访问。 在第二间隔期间，经由第一和第二外部信令接口同时访问第一存储器阵列内的第三存储位置和第二存储器阵列内的第四存储位置。

公开(公告)号：WO2010117535A3

公开(公告)日：2011-02-03

申请号：PCT/US2010026757

申请日：2010-03-10

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  BROOKS JOHN WELSFORD ,  KASAMSETTY KISHORE VEN ,  PEREGO RICHARD E

Inventor： WARE FREDERICK A ,  BROOKS JOHN WELSFORD ,  KASAMSETTY KISHORE VEN ,  PEREGO RICHARD E

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02

CPC classification number: G06F13/161

Abstract: The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device.

Abstract translation: 本实施例提供一种存储器系统，其被配置为从存储器控制器向存储器件发送请求，其中该请求包括独立的激活和预充电命令。 activate命令与一个行地址相关联，该地址标识了activate命令的第一行。 响应于激活命令，系统激活存储器设备中第一组中的第一行。 类似地，响应于预充电命令，系统对存储器件中的第二存储体进行预充电。

公开(公告)号：WO2010065290A2

公开(公告)日：2010-06-10

申请号：PCT/US2009/064813

申请日：2009-11-17

Applicant: RAMBUS INC. ,  WARE, Frederick, A. ,  RICHARDSON, Wayne ,  KASAMSETTY, Kishore

Inventor： WARE, Frederick, A. ,  RICHARDSON, Wayne ,  KASAMSETTY, Kishore

IPC: G06F13/32 ,  G06F13/24 ,  G06F11/10 ,  G06F12/00

CPC classification number: G11C29/56 ,  G01R31/3171 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50012 ,  G11C29/56012

Abstract: A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.

Abstract translation: 存储器系统包括经由高速数据和请求链路耦合到至少一个存储器设备的存储器控​​制器。 定期校准链路的时间和电压裕度，以减少误码。 高速请求链接使校准复杂化，因为通过未校准的请求链接发布的命令可能被存储器设备错误地解释。 错误解释的命令会破坏校准过程（例如，写入命令可能被错误解释为断电命令）。 内存控制器使用单独的低速控制接口来解决此问题，以发出过滤器命令，指示内存设备在校准模式下拒绝潜在的破坏性请求。