公开(公告)号：WO2013095645A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067223

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  CAPPELLANI, Annalisa ,  KUHN, Kelin J. ,  RIOS, Rafael ,  BHIMARASETTI, Gopinath ,  GHANI, Tahir ,  KIM, Seiyon

Inventor： CAPPELLANI, Annalisa ,  KUHN, Kelin J. ,  RIOS, Rafael ,  BHIMARASETTI, Gopinath ,  GHANI, Tahir ,  KIM, Seiyon

IPC: H01L21/336 ,  H01L29/78 ,  B82B3/00

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02587 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

Abstract translation: 描述了具有调制纳米线计数的半导体器件和形成这种器件的方法。 例如，半导体结构包括具有多个纳米线的第一半导体器件，该多个纳米线设置在衬底上并且堆叠在具有第一最上层纳米线的第一垂直平面中。 第二半导体器件具有设置在衬底上方的一个或多个纳米线并且堆叠在具有第二最上层纳米线的第二垂直平面中。 第二半导体器件包括比第一半导体器件少的一个或多个纳米线。 第一和第二最上层的纳米线设置在与第一和第二垂直平面正交的同一平面中。

公开(公告)号：WO2012074872A2

公开(公告)日：2012-06-07

申请号：PCT/US2011/062059

申请日：2011-11-23

Applicant: INTEL CORPORATION ,  KUHN, Kelin J. ,  KIM, Seiyon ,  RIOS, Rafael ,  CEA, Stephen M. ,  GILES, Martin D. ,  CAPPELLANI, Annalisa ,  RAKSHIT, Titash ,  CHANG, Peter ,  RACHMADY, Willy

Inventor： KUHN, Kelin J. ,  KIM, Seiyon ,  RIOS, Rafael ,  CEA, Stephen M. ,  GILES, Martin D. ,  CAPPELLANI, Annalisa ,  RAKSHIT, Titash ,  CHANG, Peter ,  RACHMADY, Willy

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract translation: 描述了形成微电子结构的方法。 那些方法的实施例包括形成包括衬底的纳米线器件，所述衬底包括与间隔物相邻的源极/漏极结构以及设置在间隔物之间​​的纳米线沟道结构，其中纳米线沟道结构垂直堆叠在彼此之上。

公开(公告)号：WO2012040075A2

公开(公告)日：2012-03-29

申请号：PCT/US2011/052084

申请日：2011-09-19

Applicant: INTEL CORPORATION ,  CEA, Stephen M. ,  KOTLYAR, Roza ,  KAVALIEROS, Jack T. ,  GILES, Martin D. ,  GHANI, Tahir ,  KUHN, Kelin J. ,  KUHN, Markus ,  ZELICK, Nancy M.

Inventor： CEA, Stephen M. ,  KOTLYAR, Roza ,  KAVALIEROS, Jack T. ,  GILES, Martin D. ,  GHANI, Tahir ,  KUHN, Kelin J. ,  KUHN, Markus ,  ZELICK, Nancy M.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

Abstract translation: 根据该方法制造的方法和装置。 该方法包括：提供包括第一材料的衬底;以及提供包括第二材料的鳍片，鳍片设置在衬底上并且具有器件有源部分，第一材料和第二材料在其各自的晶体结构之间呈现晶格失配 。 提供鳍片包括：在衬底上提供包括第二材料的双轴应变膜; 并去除部分双轴应变薄膜，从而形成基本上单轴应变的翅片。

公开(公告)号：WO2014142910A1

公开(公告)日：2014-09-18

申请号：PCT/US2013/031607

申请日：2013-03-14

Applicant: INTEL CORPORATION ,  PAWASHE, Chytra ,  KIM, Raseong ,  KIM, Seiyon ,  KUHN, Kelin J. ,  MANIPATRUNI, Sasikanth ,  RIOS, Rafael ,  YOUNG, Ian A. ,  LIN, Kevin ,  CHAUDHRY, Anurag

Inventor： PAWASHE, Chytra ,  KIM, Raseong ,  KIM, Seiyon ,  KUHN, Kelin J. ,  MANIPATRUNI, Sasikanth ,  RIOS, Rafael ,  YOUNG, Ian A. ,  LIN, Kevin ,  CHAUDHRY, Anurag

IPC: H01L29/00 ,  B81B7/00

CPC classification number: H01L29/84 ,  B82Y10/00 ,  H01H1/0094 ,  H01H9/0271 ,  H01H59/0009 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

Abstract translation: 描述了基于纳米线的机械开关装置。 例如，纳米线继电器包括设置在设置在基板上方的空隙中的纳米线。 纳米线具有锚固部分和悬挂部分。 第一栅电极邻近空隙设置，并与纳米线隔开。 第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线间隔开。

公开(公告)号：WO2014018201A1

公开(公告)日：2014-01-30

申请号：PCT/US2013/047146

申请日：2013-06-21

Applicant: INTEL CORPORATION ,  GLASS, Glenn A. ,  KUHN, Kelin J. ,  KIM, Seiyon ,  MURTHY, Anand S. ,  AUBERTINE, Daniel B.

Inventor： GLASS, Glenn A. ,  KUHN, Kelin J. ,  KIM, Seiyon ,  MURTHY, Anand S. ,  AUBERTINE, Daniel B.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract translation: 公开了用于定制纳米线晶体管器件以提供同一集成电路管芯内的不同范围的通道配置和/或材料系统的技术。 根据一个示例性实施例，除去牺牲翅片并用适合于给定应用的任意组合和应变的定制材料堆叠代替。 在一种这样的情况下，第一组牺牲散热片中的每一个凹陷或以其它方式移除并被p型层堆叠代替，并且第二组牺牲散热片中的每一个凹进或以其它方式移除， 类型层堆栈。 p型层堆栈可以完全独立于n型层堆栈的过程，反之亦然。 使用本文提供的技术可实现许多其它电路配置和设备变化。

公开(公告)号：WO2013095656A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067242

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  CAPPELLANI, Annalisa ,  TOLCHINSKY, Peter G. ,  KUHN, Kelin J. ,  GLASS, Glenn A. ,  LE, Van H.

Inventor： CAPPELLANI, Annalisa ,  TOLCHINSKY, Peter G. ,  KUHN, Kelin J. ,  GLASS, Glenn A. ,  LE, Van H.

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/045 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78687 ,  H01L29/78696

Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

Abstract translation: 描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。 例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。 第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。 半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。 第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料构成。 通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座，将第二纳米线或半导体本体与晶体衬底隔离。

公开(公告)号：WO2013154574A1

公开(公告)日：2013-10-17

申请号：PCT/US2012/033472

申请日：2012-04-13

Applicant: INTEL CORPORATION ,  CAPPELLANI, Annalisa ,  LE, Van H. ,  GLASS, Glenn A. ,  KUHN, Kelin J. ,  CEA, Stephen M.

Inventor： CAPPELLANI, Annalisa ,  LE, Van H. ,  GLASS, Glenn A. ,  KUHN, Kelin J. ,  CEA, Stephen M.

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/76 ,  H01L21/7624 ,  H01L21/76283 ,  H01L29/0603 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/7378 ,  H01L29/785 ,  H01L33/12 ,  H05K1/18

Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

Abstract translation: 公开了用于将应变诱导半导体缓冲层转变成缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括从生长出来的那些 在应变诱导缓冲器上并具有埋入的电绝缘体层。 例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。 此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。 在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

公开(公告)号：WO2013095443A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066544

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  CAPPELLANI, Annalisa ,  KUHN, Kelin J. ,  RIOS, Rafael ,  DAVILA, Aura ,  GHANI, Tahir

Inventor： CAPPELLANI, Annalisa ,  KUHN, Kelin J. ,  RIOS, Rafael ,  DAVILA, Aura ,  GHANI, Tahir

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7831 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66484

Abstract: Semiconductor devices having three-dimensional bodies with modulated heights and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed above a substrate. The first semiconductor body has a first height and an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed above the substrate. The second semiconductor body has a second height and an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar and the first and second heights are different.

Abstract translation: 描述具有调制高度的三维体的半导体器件和形成这种器件的方法。 例如，半导体结构包括具有设置在基板上方的第一半导体本体的第一半导体器件。 第一半导体本体具有第一高度和具有第一水平面的最上表面。 半导体结构还包括具有设置在衬底上方的第二半导体本体的第二半导体器件。 第二半导体本体具有第二高度和具有第二水平面的最上表面。 第一和第二水平面是共面的，第一和第二高度是不同的。

公开(公告)号：WO2015094167A1

公开(公告)日：2015-06-25

申请号：PCT/US2013/075452

申请日：2013-12-16

Applicant: INTEL CORPORATION ,  CEA, Stephen M. ,  KOTLYAR, Roza ,  KENNEL, Harold, W. ,  MURTHY, Anand, S. ,  GLASS, Glenn, A. ,  KUHN, Kelin, J. ,  GHANI, Tahir

Inventor： CEA, Stephen M. ,  KOTLYAR, Roza ,  KENNEL, Harold, W. ,  MURTHY, Anand, S. ,  GLASS, Glenn, A. ,  KUHN, Kelin, J. ,  GHANI, Tahir

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66818 ,  H01L29/7781 ,  H01L29/7782

Abstract: The embodiments herein provide semiconductor devices and methods related to strained NMOS and PMOS devices without relaxed substrates, and systems incorporating such semiconductor devices and methods therefor.

Abstract translation: 本文的实施例提供了与没有松弛衬底的应变NMOS和PMOS器件有关的半导体器件和方法，以及包含这种半导体器件的系统及其方法。

公开(公告)号：WO2013095650A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067232

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  CEA, Stephen M. ,  CAPPELLANI, Annalisa ,  GILES, Martin D. ,  RIOS, Rafael ,  KIM, Seiyon ,  KUHN, Kelin J.

Inventor： CEA, Stephen M. ,  CAPPELLANI, Annalisa ,  GILES, Martin D. ,  RIOS, Rafael ,  KIM, Seiyon ,  KUHN, Kelin J.

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/78618 ,  B82Y40/00 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/66977 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Abstract translation: 描述了具有非离散源极和漏极区域的纳米线结构。 例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。 每个纳米线包括设置在纳米线中的离散通道区域。 栅电极堆叠围绕多个垂直堆叠的纳米线。 一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。