公开(公告)号：WO2010141668A2

公开(公告)日：2010-12-09

申请号：PCT/US2010/037184

申请日：2010-06-03

Applicant: INTERMOLECULAR, INC. ,  MATZ, Laura ,  RUI, Xiangxin ,  LEI, Xinjian ,  SHANKER, Sunil ,  KIM, Moo-sung ,  FUCHIGAMI, Nobi ,  BUCHANAN, Iain ,  DUONG, Anh ,  MALHOTRA, Sandra ,  HASHIM, Imran

Inventor： MATZ, Laura ,  RUI, Xiangxin ,  LEI, Xinjian ,  SHANKER, Sunil ,  KIM, Moo-sung ,  FUCHIGAMI, Nobi ,  BUCHANAN, Iain ,  DUONG, Anh ,  MALHOTRA, Sandra ,  HASHIM, Imran

IPC: H01L21/205 ,  H01L21/31 ,  C23C16/44 ,  C23C16/40

CPC classification number: C23C16/45531 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/3142 ,  H01L21/31691 ,  H01L28/56

Abstract: Embodiments of the current invention include methods of forming a strontium titanate (SrTiO 3 ) film using atomic layer deposition (ALD). More particularly, the method includes forming a plurality of titanium oxide (TiO 2 ) unit films using ALD and forming a plurality of strontium oxide (SrO) unit films using ALD. The combined thickness of the TiO 2 and SrO unit films is less than approximately 5 angstroms. The TiO 2 and SrO units films are then annealed to form a strontium titanate layer.

Abstract translation: 本发明的实施方案包括使用原子层沉积（ALD）形成钛酸锶（SrTiO 3）膜的方法。 更具体地说，该方法包括使用ALD形成多个氧化钛（TiO 2）单元膜并使用ALD形成多个氧化锶（SrO）单元膜。 TiO 2和SrO单元膜的组合厚度小于约5埃。 然后将TiO 2和SrO单元膜退火以形成钛酸锶层。

公开(公告)号：WO2009015298A3

公开(公告)日：2009-01-29

申请号：PCT/US2008/071089

申请日：2008-07-24

Applicant: INTERMOLECULAR, INC. ,  MALHOTRA, Sandra, G. ,  KUMAR, Pragati ,  BARSTOW, Sean ,  CHIANG, Tony ,  PHATAK, Prashant, B. ,  WU, Wen ,  SHANKER, Sunil

Inventor： MALHOTRA, Sandra, G. ,  KUMAR, Pragati ,  BARSTOW, Sean ,  CHIANG, Tony ,  PHATAK, Prashant, B. ,  WU, Wen ,  SHANKER, Sunil

IPC: H01L21/8247

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

公开(公告)号：WO2011034536A1

公开(公告)日：2011-03-24

申请号：PCT/US2009/057371

申请日：2009-09-18

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC. ,  KUMAR, Pragati ,  CHEN, Hanhong ,  FUCHIGAMI, Nobi ,  SHANKER, Sunil ,  MALHOTRA, Sandra ,  HASHIM, Imran

Inventor： KUMAR, Pragati ,  CHEN, Hanhong ,  FUCHIGAMI, Nobi ,  SHANKER, Sunil ,  MALHOTRA, Sandra ,  HASHIM, Imran

IPC: H01L27/04 ,  H01L27/108

CPC classification number: C23C16/45531 ,  C23C16/0272 ,  C23C16/0281 ,  C23C16/405 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02304 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/65 ,  H01L28/75

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness ("EOT").

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，要生长电介质层的底部电极可以具有钌基表面。 钌表面与电介质层的晶格匹配（例如氧化钛，钛酸锶钛酸钡或钛酸钡锶）​​有助于促进金红石相氧化钛的生长，从而导致较高的介电常数和较低的有效氧化物厚度。 钌基材料还提供高功函数材料，导致较低的泄漏。 为了减轻与使用钌有关的成核延迟，可以采用基于钛的粘附层或胶层。 可以进一步采用预处理工艺，以增加有效的电容器板面积，从而进一步提高介电常数和有效的氧化物厚度（“EOT”）。

公开(公告)号：WO2009131902A3

公开(公告)日：2010-03-11

申请号：PCT/US2009040902

申请日：2009-04-17

Applicant: INTERMOLECULAR INC ,  ELPIDA MEMORY INC ,  HASHIM IMRAN ,  DE INDRANIL ,  CHIANG TONY ,  HAYWOOD EDWARD ,  CHEN HANHONG ,  FUCHIGAMI NOBI ,  KUMAR PRAGATI ,  MALHOTRA SANDRA ,  SHANKER SUNIL

Inventor： HASHIM IMRAN ,  DE INDRANIL ,  CHIANG TONY ,  HAYWOOD EDWARD ,  CHEN HANHONG ,  FUCHIGAMI NOBI ,  KUMAR PRAGATI ,  MALHOTRA SANDRA ,  SHANKER SUNIL

IPC: H01L21/8242 ,  H01L21/205 ,  H01L21/31 ,  H01L27/108

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，氧化物层可以通过PVD工艺或者通过使用特定前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产 反应。

公开(公告)号：WO2009135182A2

公开(公告)日：2009-11-05

申请号：PCT/US2009042611

申请日：2009-05-01

Applicant: INTERMOLECULAR INC ,  SHANKER SUNIL ,  CHIANG TONY

Inventor： SHANKER SUNIL ,  CHIANG TONY

IPC: H01L21/205

CPC classification number: C23C16/047 ,  C23C16/04 ,  C23C16/45536 ,  C23C16/45551 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/45591 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/50 ,  C23C16/5096 ,  C23C16/52 ,  H01J37/32357 ,  H01J37/32366

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

Abstract translation: 描述组合等离子体增强沉积技术，包括指定衬底的多个区域，为多个区域的至少第一区域提供前体，以及向第一区域提供等离子体，以将第一材料沉积在使用 第一前体，其中所述第一材料不同于形成在所述基底的第二区域上的第二材料。

公开(公告)号：WO2009032958A1

公开(公告)日：2009-03-12

申请号：PCT/US2008/075301

申请日：2008-09-05

Applicant: INTERMOLECULAR, INC. ,  CHIANG, Tony, P. ,  SHANKER, Sunil ,  LANG, Chi-I

Inventor： CHIANG, Tony, P. ,  SHANKER, Sunil ,  LANG, Chi-I

IPC: H01L21/205

CPC classification number: C23C16/45574 ,  C23C16/45544 ,  C23C16/45548

Abstract: A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings.

Abstract translation: 提供组合处理室和方法。 在该方法中，流体体积在衬底的表面上流动，具有不同部分的流体体积具有不同构成组分，以同时将衬底的偏析区域暴露于与构成组分的混合物中，所述构成组分与相邻区域暴露于其中的构成组分不同 。 通过多个流动产生不同处理的分离区域。

公开(公告)号：WO2009015298A2

公开(公告)日：2009-01-29

申请号：PCT/US2008071089

申请日：2008-07-24

Applicant: INTERMOLECULAR INC ,  MALHOTRA SANDRA G ,  KUMAR PRAGATI ,  BARSTOW SEAN ,  CHIANG TONY ,  PHATAK PRASHANT B ,  WU WEN ,  SHANKER SUNIL

Inventor： MALHOTRA SANDRA G ,  KUMAR PRAGATI ,  BARSTOW SEAN ,  CHIANG TONY ,  PHATAK PRASHANT B ,  WU WEN ,  SHANKER SUNIL

IPC: H01L21/8247

CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract translation: 提供基于电阻切换存储器元件层的非易失性存储器元件。 非易失性存储器元件可以具有电阻式开关金属氧化物层。 电阻切换金属氧化物层可以具有一个或多个氧化物层。 电阻式开关金属氧化物可掺杂有增加其熔化温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。

公开(公告)号：WO2010141668A3

公开(公告)日：2011-03-03

申请号：PCT/US2010037184

申请日：2010-06-03

Applicant: INTERMOLECULAR INC ,  MATZ LAURA ,  RUI XIANGXIN ,  LEI XINJIAN ,  SHANKER SUNIL ,  KIM MOO-SUNG ,  FUCHIGAMI NOBI ,  BUCHANAN IAIN ,  DUONG ANH ,  MALHOTRA SANDRA ,  HASHIM IMRAN

Inventor： MATZ LAURA ,  RUI XIANGXIN ,  LEI XINJIAN ,  SHANKER SUNIL ,  KIM MOO-SUNG ,  FUCHIGAMI NOBI ,  BUCHANAN IAIN ,  DUONG ANH ,  MALHOTRA SANDRA ,  HASHIM IMRAN

IPC: H01L21/205 ,  C23C16/40 ,  C23C16/44 ,  H01L21/31

CPC classification number: C23C16/45531 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/3142 ,  H01L21/31691 ,  H01L28/56

Abstract: Embodiments of the current invention include methods of forming a strontium titanate (SrTiO3) film using atomic layer deposition (ALD). More particularly, the method includes forming a plurality of titanium oxide (TiO2) unit films using ALD and forming a plurality of strontium oxide (SrO) unit films using ALD. The combined thickness of the TiO2 and SrO unit films is less than approximately 5 angstroms. The TiO2 and SrO units films are then annealed to form a strontium titanate layer.

Abstract translation: 本发明的实施方案包括使用原子层沉积（ALD）形成钛酸锶（SrTiO 3）膜的方法。 更具体地说，该方法包括使用ALD形成多个氧化钛（TiO 2）单元膜并使用ALD形成多个氧化锶（SrO）单元膜。 TiO 2和SrO单元膜的组合厚度小于约5埃。 然后将TiO 2和SrO单元膜退火以形成钛酸锶层。

公开(公告)号：WO2009135182A3

公开(公告)日：2009-11-05

申请号：PCT/US2009/042611

申请日：2009-05-01

Applicant: INTERMOLECULAR, INC. ,  SHANKER, Sunil ,  CHIANG, Tony

Inventor： SHANKER, Sunil ,  CHIANG, Tony

IPC: H01L21/205

Abstract: Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate.

公开(公告)号：WO2009131902A2

公开(公告)日：2009-10-29

申请号：PCT/US2009/040902

申请日：2009-04-17

Applicant: INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC. ,  HASHIM, Imran ,  DE, Indranil ,  CHIANG, Tony ,  HAYWOOD, Edward ,  CHEN, Hanhong ,  FUCHIGAMI, Nobi ,  KUMAR, Pragati ,  MALHOTRA, Sandra ,  SHANKER, Sunil

Inventor： HASHIM, Imran ,  DE, Indranil ,  CHIANG, Tony ,  HAYWOOD, Edward ,  CHEN, Hanhong ,  FUCHIGAMI, Nobi ,  KUMAR, Pragati ,  MALHOTRA, Sandra ,  SHANKER, Sunil

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/31 ,  H01L21/205

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract translation: 本公开内容提供（a）制造基于钇和钛的氧化物层（例如电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，氧化物层可以通过PVD工艺或者通过使用特定前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产 反应。