公开(公告)号：WO2010032599A1

公开(公告)日：2010-03-25

申请号：PCT/JP2009/065019

申请日：2009-08-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  ABE, Takayuki ,  TAKAHASHI, Yasuyuki

Inventor： ABE, Takayuki ,  TAKAHASHI, Yasuyuki

IPC: H01L27/10

CPC classification number: H01L27/11206 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/49855 ,  H01L23/5227 ,  H01L23/5252 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/66 ,  H01L24/24 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/112 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/94 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor.

Abstract translation: 提供了包括存储单元的半导体器件。 存储单元包括晶体管，存储元件和电容器。 存储元件的第一和第二电极之一和电容器的第一和第二电极中的一个由相同的金属膜形成。 用作存储元件的第一和第二电极中的一个的金属膜和电容器的第一和第二电极之一的金属膜与用作电容器的第一和第二电极中的另一个的膜重叠。

公开(公告)号：WO1984001270A1

公开(公告)日：1984-04-12

申请号：PCT/JP1983000320

申请日：1983-09-29

Applicant: MEIJI MILK PRODUCTS COMPANY LIMITED ,  TAKAHASHI, Yasuyuki ,  YOSHIDA, Toshiro ,  TAKAHASHI, Takeshi

Inventor： MEIJI MILK PRODUCTS COMPANY LIMITED

IPC: A23L01/19

CPC classification number: A23L29/10

Abstract: A process for producing an extremely fine and stable W/O/W composite emulsion, which comprises preparing a fine W/O emulsion by a primary emulsification using polyglycerol-condensed ricinoleic ester and a secondary emulsification of adding an aqueous phase containing an emulsifier to the resulting W/O emulsion and subsequent stirring.

公开(公告)号：WO2010035626A1

公开(公告)日：2010-04-01

申请号：PCT/JP2009/065549

申请日：2009-09-01

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  MATSUMOTO, Chikako ,  TAKAHASHI, Yasuyuki

Inventor： MATSUMOTO, Chikako ,  TAKAHASHI, Yasuyuki

IPC: H01L21/822 ,  H01L27/04 ,  H01L29/861

CPC classification number: G06K19/0723 ,  G06K19/0707 ,  H01L27/0207

Abstract: To easily detect in a semiconductor device whether a voltage within the specifications of the semiconductor device is obtained. The semiconductor device includes a detecting circuit that detects an output voltage of an inner circuit of the semiconductor device and judges whether the output voltage is within or out of the specifications of the semiconductor device. A signal for determining whether an output voltage is within or out of the specifications is transmitted from the detecting circuit to a digital circuit, and the digital circuit performs or stops circuit operation in accordance with the signal.

Abstract translation: 为了容易地在半导体器件中检测是否获得了半导体器件的规格内的电压。 半导体器件包括检测电路，该检测电路检测半导体器件的内部电路的输出电压，并判断输出电压是否在半导体器件的规范之内或之外。 用于确定输出电压是否在规格范围内的信号从检测电路发送到数字电路，并且数字电路根据该信号执行或停止电路操作。

公开(公告)号：WO2011125455A1

公开(公告)日：2011-10-13

申请号：PCT/JP2011/056510

申请日：2011-03-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  SAITO, Toshihiko ,  TAKAHASHI, Yasuyuki

Inventor： SAITO, Toshihiko ,  TAKAHASHI, Yasuyuki

IPC: G11C17/14

CPC classification number: G11C7/12 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/1214

Abstract: A semiconductor memory device or a semiconductor device which has high reading accuracy is provided. A bit line, a word line, a memory cell placed in an intersection portion of the bit line and the word line, and a reading circuit electrically connected to the bit line are provided. The memory cell includes a first transistor and an antifuse. The reading circuit includes a pre-charge circuit, a clocked inverter, and a switch. The pre-charge circuit includes a second transistor and a NAND circuit. The semiconductor memory device includes transistor in each of which an oxide semiconductor is used in a channel formation region, as the first transistor and the second transistor.

Abstract translation: 提供了具有高读取精度的半导体存储器件或半导体器件。 提供位线，字线，放置在位线和字线的交叉部分中的存储单元，以及电连接到位线的读取电路。 存储单元包括第一晶体管和反熔丝。 读取电路包括预充电电路，时钟反相器和开关。 预充电电路包括第二晶体管和NAND电路。 半导体存储器件包括在沟道形成区域中使用氧化物半导体作为第一晶体管和第二晶体管的晶体管。

公开(公告)号：WO2011093003A1

公开(公告)日：2011-08-04

申请号：PCT/JP2010/073903

申请日：2010-12-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  TAKAHASHI, Yasuyuki ,  SAITO, Toshihiko

Inventor： TAKAHASHI, Yasuyuki ,  SAITO, Toshihiko

IPC: H01L27/105 ,  G11C11/405 ,  G11C14/00 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/088 ,  H01L27/108 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C2216/26 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/1225

Abstract: It is to provide a semiconductor memory device in which high voltage is not needed in writing, a defect is less likely to occur, the writing time is short, and data cannot be rewritten without an increase in cost. The semiconductor memory device includes a memory element which includes a diode-connected first transistor, a second transistor whose gate is connected to one terminal of a source electrode and a drain electrode of the diode-connected first transistor, and a capacitor connected to the one terminal of the source electrode and the drain electrode of the diode-connected first transistor and the gate of the second transistor.

Abstract translation: 提供一种在写入时不需要高电压的半导体存储器件，不太可能发生缺陷，写入时间短，并且在不增加成本的情况下不能重写数据。 该半导体存储器件包括存储元件，该存储元件包括二极管连接的第一晶体管，第二晶体管的栅极连接到源电极的一个端子和二极管连接的第一晶体管的漏极，以及连接到该二极管的第一晶体管的电容器 二极管连接的第一晶体管的源电极和漏电极以及第二晶体管的栅极。

公开(公告)号：WO1985004346A1

公开(公告)日：1985-10-10

申请号：PCT/JP1985000143

申请日：1985-03-25

Applicant: MEIJI MILK PRODUCTS COMPANY LIMITED ,  TAKAHASHI, Yasuyuki ,  YOSHIDA, Toshiro ,  TAKAHASHI, Takeshi

Inventor： MEIJI MILK PRODUCTS COMPANY LIMITED

IPC: B01J13/00

CPC classification number: A61K8/39 ,  A61K8/066 ,  A61K9/0014 ,  A61K9/113 ,  A61K47/14 ,  A61Q5/00 ,  A61Q19/00 ,  A61Q19/10 ,  B01F3/0811 ,  B01F17/0028 ,  B01F2003/0838 ,  Y10S514/844 ,  Y10S514/845 ,  Y10S514/846 ,  Y10S514/847 ,  Y10S514/848 ,  Y10S514/873 ,  Y10S514/88 ,  Y10S514/881 ,  Y10S514/937 ,  Y10S514/938 ,  Y10S514/943 ,  Y10S514/969 ,  Y10S516/925

Abstract: A process for preparing a W/O/W complex emulsion using polyglycerin-condensed ricinoleic ester. This process enables to remarkably raise the yield of W/O/W complex emulsion. The resulting complex emulsion is stable for a long time, and has excellent heat stability, thus being extremely useful in the field of medicines and cosmetics.