公开(公告)号：WO2018022185A1

公开(公告)日：2018-02-01

申请号：PCT/US2017/034890

申请日：2017-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： BARASKAR, Ashish ,  MAKALA, Raghuveer S. ,  LU, Ching-Huang ,  LEE, Yao-Sheng ,  CHEN, Jian

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

Abstract translation: 三维非易失性存储器包括多个字线层，所述多个字线层交替地与衬底上的堆叠中的多个介电层布置。 较高的字线被实现为比较低的字线更厚，以便减少字线之间的电阻变化。

公开(公告)号：WO2017112196A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/062954

申请日：2016-11-18

Applicant: INTEL CORPORATION

Inventor： BERNHARDT, Michael J. ,  KIM, Yudong ,  FROST, Denzil S. ,  ALLEN, III, Tuman Earl ,  BAKER, Kevin Lee ,  YASTREBENETSKY, Kolya ,  WEIMER, Ronald Allen

IPC: H01L27/115

CPC classification number: H01L27/2481 ,  H01L21/31133 ,  H01L21/76837 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53295 ,  H01L24/16 ,  H01L27/105 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16113 ,  H01L2224/16157 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于存储器设备的技术和配置，该存储器设备包括具有设置在裸片的存储器区域中的多个字线的存储器阵列。 填充区域可以设置在多条字线的各对相邻字线之间。 填充区域可以包括设置在第一介电层上的第一介电层和第二介电层。 第一电介质层可以包括有机（例如，基于碳的）旋涂电介质材料（CSOD）。 第二电介质层可以包括与第一电介质层不同的电介质材料，例如无机电介质材料。 其他实施例可以被描述和/或要求保护。

公开(公告)号：WO2016128853A1

公开(公告)日：2016-08-18

申请号：PCT/IB2016/050388

申请日：2016-01-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： TAMURA, Hikaru ,  TSUTSUI, Naoaki ,  ISOBE, Atsuo

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/532 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0688 ,  H01L27/1207 ,  H01L27/1274 ,  H01L29/7869 ,  H03K19/0008

Abstract: To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

Abstract translation: 提供包括堆叠的元件层的半导体器件。 第一布线层和第二布线层堆叠在第一元件层和第二元件层之间。 在第二元件层上堆叠第三布线层和第四布线层。 逻辑单元的晶体管设置在第一元件层中。 逻辑单元的布线设置在第一布线层或第二布线层中。 逻辑单元的输入端口和输出端口设置在第三布线层中。 一个逻辑单元的输入端口通过第三布线层或第四布线层的布线连接到另一逻辑单元的输出端口。 通过第二元件层上的布线层连接逻辑单元提高了布置和连接逻辑单元的步骤的效率。

公开(公告)号：WO2013159807A1

公开(公告)日：2013-10-31

申请号：PCT/EP2012/057404

申请日：2012-04-23

Applicant: TELEDYNE DALSA B.V. ,  PEEK, Hermanus Leonardus ,  MAES, Willem, Hendrik ,  KLAASSENS, Wilco

Inventor： PEEK, Hermanus Leonardus ,  MAES, Willem, Hendrik ,  KLAASSENS, Wilco

IPC: H01L27/146

CPC classification number: H01L23/538 ,  H01L21/743 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76892 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L23/5386 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14806 ,  H01L27/14812 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a semiconductor device comprising: i) a substrate (1) comprising an insulating layer (2), wherein the electrically insulating layer (2) comprises a recess (99), and ii) a first conductive wire (20). The first conductive wire (20) comprises a first conductive sub-layer (22) provided within the recess (99), and comprises a second conductive sub-layer (24) provided on the first conductive sub-layer (22) forming a shunt for the first conductive sub-layer (22), wherein the first conductive sub-layer (22) comprises tungsten and the second conductive sub-layer (24) comprises aluminum, wherein the first conductive sub-layer (22) and the second conductive sub-layer (24) are substantially planar, and wherein the second conductive sub-layer (24) has substantially the same pattern as the first conductive sub-layer (22). The invention provides a semiconductor device, wherein the charge transport problem is improved, while ensuring a large packing density and a full flat-topology. This advantage is particularly useful in high-speed and/or high resolution image sensors.

Abstract translation: 本发明涉及一种半导体器件，包括：i）包括绝缘层（2）的衬底（1），其中电绝缘层（2）包括凹部（99），以及ii）第一导线（20）。 第一导电线（20）包括设置在凹部（99）内的第一导电子层（22），并且包括设置在第一导电子层（22）上的第二导电子层（24），形成分流 对于所述第一导电子层（22），其中所述第一导电子层（22）包括钨，并且所述第二导电子层（24）包括铝，其中所述第一导电子层（22）和所述第二导电子层 子层（24）基本上是平面的，并且其中第二导电子层（24）具有与第一导电子层（22）基本相同的图案。 本发明提供一种半导体器件，其中电荷输送问题得到改善，同时确保了大的封装密度和全平面拓扑结构。 该优点在高速和/或高分辨率图像传感器中特别有用。

公开(公告)号：WO2010032599A1

公开(公告)日：2010-03-25

申请号：PCT/JP2009/065019

申请日：2009-08-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  ABE, Takayuki ,  TAKAHASHI, Yasuyuki

Inventor： ABE, Takayuki ,  TAKAHASHI, Yasuyuki

IPC: H01L27/10

CPC classification number: H01L27/11206 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/49855 ,  H01L23/5227 ,  H01L23/5252 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/66 ,  H01L24/24 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/112 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/94 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor.

Abstract translation: 提供了包括存储单元的半导体器件。 存储单元包括晶体管，存储元件和电容器。 存储元件的第一和第二电极之一和电容器的第一和第二电极中的一个由相同的金属膜形成。 用作存储元件的第一和第二电极中的一个的金属膜和电容器的第一和第二电极之一的金属膜与用作电容器的第一和第二电极中的另一个的膜重叠。

公开(公告)号：WO2010002718A2

公开(公告)日：2010-01-07

申请号：PCT/US2009048764

申请日：2009-06-26

Applicant: INTEL CORP ,  SELL BERNHARD ,  GOLONZKA OLEG

Inventor： SELL BERNHARD ,  GOLONZKA OLEG

IPC: H01L21/28

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IlD disposed on a top surface of a metal gate disposed on the substrate.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：WO2008027278A2

公开(公告)日：2008-03-06

申请号：PCT/US2007018646

申请日：2007-08-23

Applicant: MICRON TECHNOLOGY INC ,  JUN LIU

Inventor： JUN LIU

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/52 ,  H01L21/76849 ,  H01L21/76886 ,  H01L23/53257 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements.

Abstract translation: PCRAM电池具有高电阻率底部电极帽，以在电池和底部电极之间的界面附近提供部分加热，防止非晶GST区域与底部电极分离，并减少编程电流要求。

公开(公告)号：WO2005122255A1

公开(公告)日：2005-12-22

申请号：PCT/US2005/019429

申请日：2005-06-02

Applicant: EASTMAN KODAK COMPANY ,  TAN, Liang ,  ERHARDT, Herbert, James

Inventor： TAN, Liang ,  ERHARDT, Herbert, James

IPC: H01L23/58

CPC classification number: H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.

Abstract translation: 集成电路包括基板; 跨越衬底的周边的密封元件，其形成用于衬底的保护性边界; 在保护边界内包含至少两个不同层的跨越衬底的多条铜线; 设置在密封元件外部的第一导电元件; 以及一个或多个第二导电元件，其连接铜线中的至少两条并跨过密封元件; 其中所述导电元件是耐氧化的并且将所述铜线连接到所述第一导电元件的基本上非氧化性金属。

公开(公告)号：WO1997030476A1

公开(公告)日：1997-08-21

申请号：PCT/US1997002278

申请日：1997-02-12

Applicant: ALLIEDSIGNAL INC.

Inventor： ALLIEDSIGNAL INC. ,  GOETZ, George, Gabriel ,  DAWSON, Warren, Michael

IPC: H01L21/768

CPC classification number: H01L23/53257 ,  H01L21/76838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chromium/refractory metal alloy deposited thin film conductor (14) for use in high temperature semiconductor integrated circuit electronics suitable for operating temperatures as high as 400 DEG C. The thin film conductor (14) can be formed from a chromium tungsten alloy layer deposited on an integrated circuit surface (12). The chromium tungsten layer is then etched to form the desired conductor (10) pattern. The deposited chromium tungsten thin film conductor (10) is then heated in an atmosphere of hydrogen containing some water vapor, causing some of the chromium to diffuse to the surface and oxidize. This produces an excellent conformal passivating film (11) of Cr2O3. This also produces excellent adhesion to SiO2 and Si3N4. Further, the Cr enhances the surface mobility of sputter deposited refractory metal atoms yielding large, nonfibrous grains which enhance conformal step coverage and reduces electromigration.

Abstract translation: 一种用于高温半导体集成电路电路的铬/难熔金属合金沉积薄膜导体（14），适用于高达400℃的工作温度。薄膜导体（14）可以由沉积在其上的铬钨合金层形成 在集成电路表面（12）上。 然后蚀刻铬钨层以形成所需的导体（10）图案。 然后将沉积的铬钨薄膜导体（10）在含有一些水蒸汽的氢气气氛中加热，导致一些铬扩散到表面并氧化。 这产生了优良的Cr 2 O 3的保形钝化膜（11）。 这也对SiO 2和Si 3 N 4产生优异的粘附性。 此外，Cr增强溅射沉积的难熔金属原子的表面迁移率，产生大的非纤维颗粒，这增强了适形步骤覆盖并减少了电迁移。

公开(公告)号：WO2018126256A2

公开(公告)日：2018-07-05

申请号：PCT/US2018/012022

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： LIU, Jun ,  HALLER, Gordon A. ,  WANG, Fei ,  NG, Wei Yeeng ,  MCKINSEY, Wesley O. ,  XIE, Zhiqiang ,  ADAMS, Jeremy F. ,  ZHU, Hongbin ,  ZHAO, Jun ,  LEVAN, Mark A.

IPC: H01L27/11573 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/76831 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53214 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.