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    LDMOS TRANSISTOR
    1.
    发明申请
    LDMOS TRANSISTOR 审中-公开

    公开(公告)号：WO2007017803A3

    公开(公告)日：2007-02-15

    申请号：PCT/IB2006/052644

    申请日：2006-08-02

    Applicant: NXP B.V. ,  ZAWILSKI, Peter ,  THEEUWEN, Stephan, J., C., H. ,  VAN RIJS, Freerk ,  HAMMES, Petra, C., A.

    Inventor： THEEUWEN, Stephan, J., C., H. ,  VAN RIJS, Freerk ,  HAMMES, Petra, C., A.

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L23/482 ,  H01L23/532

    Abstract: The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and a drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2μm. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.

    LDMOS TRANSISTOR
    3.
    发明申请
    LDMOS TRANSISTOR 审中-公开
    LDMOS晶体管

    公开(公告)号：WO2007017803A2

    公开(公告)日：2007-02-15

    申请号：PCT/IB2006052644

    申请日：2006-08-02

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  ZAWILSKI PETER ,  THEEUWEN STEPHAN J C H ,  VAN RIJS FREERK ,  HAMMES PETRA C A

    Inventor： THEEUWEN STEPHAN J C H ,  VAN RIJS FREERK ,  HAMMES PETRA C A

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

    CPC classification number: H01L29/41758 ,  H01L21/76895 ,  H01L23/4827 ,  H01L23/53219 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and a drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2µm. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.

    Abstract translation: 本发明的LDMOS晶体管（1）包括基板（2），栅极电极（10），基板接触区域（11），源极区域（3），沟道区域（4）和漏极区域 ），该漏极区（5）包括漏极接触区（6）和漏极延伸区（7）。 漏极接触区域（6）电连接到在漏极延伸区域（7）上延伸的顶部金属层（23），顶部金属层（23）和漏极延伸区域（23）之间的距离（723） 7）大于2μm。 这样可以减小漏极接触区域（6）的面积，并且增加LDMOS晶体管（1）的RF功率输出效率。 在另一个实施例中，源极区（3）经由硅化物层（32）而不是第一金属层（21）电连接到衬底接触区（11），从而减小源区（3）和 漏极区域（5），从而进一步提高LDMOS晶体管（1）的RF功率输出效率。

    LDMOS TRANSISTOR
    4.
    发明申请
    LDMOS TRANSISTOR 审中-公开
    LDMOS晶体管

    公开(公告)号：WO2007007273A2

    公开(公告)日：2007-01-18

    申请号：PCT/IB2006/052325

    申请日：2006-07-10

    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  ZAWILSKI, Peter ,  VAN RIJS, Freerk ,  THEEUWEN, Stephan, J., C., H. ,  HAMMES, Petra, C., A.

    Inventor： VAN RIJS, Freerk ,  THEEUWEN, Stephan, J., C., H. ,  HAMMES, Petra, C., A.

    CPC classification number: H01L29/0847 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).

    Abstract translation: 本发明的LDMOS晶体管（1）包括源极区（3），沟道区（4），漏极延伸区（7）和栅电极（10）。 LDMOS晶体管（1）还包括比第一栅极氧化物层（8）厚的第一栅极氧化物层（8）和第二栅极氧化物层（9）。 第一栅极氧化物层（8）至少在沟道区（4）的与源极区（3）相邻的第一部分上延伸。 第二栅极氧化物层（9）在电场（E）的局部最大值（A，B）产生热载流子的区域上延伸，由此减小热载流子的影响并减少Idq退化。 在另一实施例中，第二栅极氧化物层（9）在沟道区（4）的第二部分上延伸，沟道区（4）的第二部分相互连接漏极延伸区（7）和沟道区（4）的第一部分，从而改善线性 LDMOS晶体管（1）的效率。

    SEMICONDUCTOR DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR AND METHOD OF OPERATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR AND METHOD OF OPERATING THE SAME 审中-公开
    包含场效应晶体管的半导体器件及其操作方法

    公开(公告)号：WO2004095577A2

    公开(公告)日：2004-11-04

    申请号：PCT/IB2004050474

    申请日：2004-04-21

    Applicant: KONINKL PHILIPS ELECTRONICS NV ,  GAJADHARSING RADJINDREPERSAD ,  ROEDLE THOMAS C ,  HAMMES PETRA C A ,  THEEUWEN STEPHAN J C H

    Inventor： GAJADHARSING RADJINDREPERSAD ,  ROEDLE THOMAS C ,  HAMMES PETRA C A ,  THEEUWEN STEPHAN J C H

    IPC: H01L27/06 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

    CPC classification number: H01L29/402 ,  H01L23/4824 ,  H01L27/0629 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: The invention relates to in particular a lateral DMOST with a drain extension (8). In the known transistor a further metal strip (20) is positioned between the gate electrode contact strip and the drain contact (16) which is electrically connected with the source region contact (15). In the device proposed here, the connection between the further metal strip (20) and the source contact (15,12) comprises a capacitor (30) and the further metal strip (20) is provided with a further contact region (35) for delivering a voltage to the further metal strip (20). In this way an improved linearity is possible and the usefulness of the device is improved in particular at high power and at high frequencies. Preferably the capacitor (30) is integrated with the transistor in a single semiconductor body (1). The invention further comprises a method of operating a device (10) according to the invention.

    Abstract translation: 本发明尤其涉及具有漏极延伸部（8）的横向DMOST。 在已知的晶体管中，另外的金属条（20）位于与源区触点（15）电连接的栅电极接触条和漏触点（16）之间。 在这里提出的装置中，另外的金属条（20）和源极触点（15,12）之间的连接包括一个电容器（30），另一个金属带（20）设置有另外的接触区域（35），用于 向另外的金属条（20）传送电压。 以这种方式，改进的线性度是可能的，并且特别是在高功率和高频下改进了器件的有用性。 优选地，电容器（30）在单个半导体本体（1）中与晶体管集成。 本发明还包括操作根据本发明的设备（10）的方法。

    LDMOS TRANSISTOR
    6.
    发明申请
    LDMOS TRANSISTOR 审中-公开
    LDMOS晶体管

    公开(公告)号：WO2009144616A1

    公开(公告)日：2009-12-03

    申请号：PCT/IB2009/052080

    申请日：2009-05-19

    Applicant: NXP B.V. ,  THEEUWEN, Stephan, J., C., H. ,  VAN RIJS, Freerk

    Inventor： THEEUWEN, Stephan, J., C., H. ,  VAN RIJS, Freerk

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L23/485 ,  H01L23/482 ,  H01L23/522 ,  H01L23/532 ,  H01L21/336 ,  H01L21/225

    CPC classification number: H01L29/7835 ,  H01L21/2257 ,  H01L21/76895 ,  H01L23/552 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An LDMOS transistor (100) on a substrate (70a, 70b) of a first conductivity type, comprises a first source region (10a), a second source region (10b) both with a source portion (73) and a common drain region (112, 212). The source portions and common drain region are of a second conductivity type opposite to the first conductivity type. The source portions and the common drain region are mutually connected through respective channel region (28a, 28b) in the substrate over which respective gate electrodes (14a, 14b) extend. The common drain region is a compound drain region comprising a first drain region (112), a second drain region (212).An isolation region (130) separating the first drain region from the second drain region by a separating distance (S) is provided in said common drain region to allow decoupling of the output capacitance and the thermal properties.

    Abstract translation: 在第一导电类型的衬底（70a，70b）上的LDMOS晶体管（100）包括第一源极区（10a），第二源极区（10b），源极部分（73）和共同漏极区域 112,212）。 源极部分和公共漏极区域是与第一导电类型相反的第二导电类型。 源极部分和公共漏极区域通过各个栅电极（14a，14b）延伸的衬底中的相应沟道区域（28a，28b）相互连接。 公共漏极区是包括第一漏极区（112），第二漏极区（212）的化合物漏极区域，将第一漏极区域与第二漏极区域分离距离（S）的隔离区域（130） 设置在所述公共漏极区域中以允许输出电容和热性质的去耦。

    LDMOS TRANSISTOR
    8.
    发明申请
    LDMOS TRANSISTOR 审中-公开
    LDMOS晶体管

    公开(公告)号：WO2009144617A1

    公开(公告)日：2009-12-03

    申请号：PCT/IB2009/052082

    申请日：2009-05-19

    Applicant: NXP B.V. ,  THEEUWEN, Stephan, J., C., H. ,  PEUSCHER, Henk, J. ,  VAN DEN HEUVEL, Rene ,  BRON, Paul

    Inventor： THEEUWEN, Stephan, J., C., H. ,  PEUSCHER, Henk, J. ,  VAN DEN HEUVEL, Rene ,  BRON, Paul

    IPC: H01L29/78 ,  H01L29/45 ,  H01L21/336 ,  H01L29/417 ,  H01L29/40 ,  H01L21/225 ,  H01L23/482 ,  H01L23/532

    CPC classification number: H01L29/7835 ,  H01L21/2257 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/522 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66659 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An LDMOS transistor (100) on a substrate (70a, 70b) of a first conductivity type, comprises a source region (10) with a source portion (73) and a drain region (12). The source portion and drain region are of a second conductivity type opposite to the first conductivity type and are mutually connected through a channel region (28) in the substrate over which a gate electrode (14) extends. The drain region comprises a drain contact region (16) and a drain extension region (15) which extends from the channel region (28) towards the drain contact region. The drain contact region is electrically connected to a top metal layer (22) by a drain contact (20), and a poly-Si drain contact layer (80) is arranged as a first contact material in between the drain contact region and the drain contact in a contact opening (51) of a first dielectric layer (52) deposited on the surface of the drain region. The poly-Si drain contact layer comprises a dopant element of the second conductivity type which is diffused therefrom through annealing to form said drain contact region.

    Abstract translation: 在第一导电类型的衬底（70a，70b）上的LDMOS晶体管（100）包括具有源极部分（73）和漏极区域（12）的源极区域（10）。 源区和漏区具有与第一导电类型相反的第二导电类型，并且通过栅极电极（14）延伸的衬底中的沟道区（28）相互连接。 漏极区域包括漏极接触区域（16）和从沟道区域（28）向漏极接触区域延伸的漏极延伸区域（15）。 漏极接触区域通过漏极接触（20）与顶部金属层（22）电连接，并且多晶硅漏极接触层（80）作为第一接触材料布置在漏极接触区域和漏极 在沉积在漏极区域的表面上的第一介电层（52）的接触开口（51）中接触。 多晶硅漏极接触层包括第二导电类型的掺杂元素，其通过退火从其扩散以形成所述漏极接触区域。

    LDMOS TRANSISTOR
    9.
    发明申请
    LDMOS TRANSISTOR 审中-公开
    LDMOS晶体管

    公开(公告)号：WO2007007273A3

    公开(公告)日：2007-10-11

    申请号：PCT/IB2006052325

    申请日：2006-07-10

    Applicant: NXP BV ,  ZAWILSKI PETER ,  VAN RIJS FREERK ,  THEEUWEN STEPHAN J C H ,  HAMMES PETRA C A

    Inventor： VAN RIJS FREERK ,  THEEUWEN STEPHAN J C H ,  HAMMES PETRA C A

    IPC: H01L29/78 ,  H01L21/336 ,  H01L23/31 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423

    CPC classification number: H01L29/66659 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/7835

    Abstract: The LDMOS transistor (1) of the invention comprises a source region (3), a channel region (4), a drain extension region (7) and a gate electrode (10). The LDMOS transistor (1) further comprises a first gate oxide layer (8) and a second gate oxide layer (9), which is thicker than the first gate oxide layer (8). The first gate oxide layer (8) at least extends over a first portion of the channel region (4), which is adjacent to the source region (3). The second gate oxide layer (9) extends over a region where a local maximum (A, B) of the electric field (E) generates hot carriers thereby reducing the impact of the hot carriers and reducing the Idq-degradation. In another embodiment the second gate oxide layer (9) extends over a second portion of the channel region (4), which mutually connects the drain extension region (7) and the first portion of the channel region (4), thereby improving the linear efficiency of the LDMOS transistor (1).

    Abstract translation: 本发明的LDMOS晶体管（1）包括源极区（3），沟道区（4），漏极延伸区（7）和栅电极（10）。 LDMOS晶体管（1）还包括比第一栅极氧化物层（8）厚的第一栅极氧化物层（8）和第二栅极氧化物层（9）。 第一栅极氧化物层（8）至少延伸在与源极区域（3）相邻的沟道区域（4）的第一部分上。 第二栅极氧化物层（9）在电场（E）的局部最大值（A，B））产生热载流子的区域上延伸，从而减少热载流子的影响并降低Idq降解。 在另一个实施例中，第二栅极氧化物层（9）在沟道区域（4）的第二部分上延伸，沟道区域（4）相互连接漏极延伸区域（7）和沟道区域（4）的第一部分，从而改善线性 LDMOS晶体管（1）的效率。

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