公开(公告)号：WO2007001294A8

公开(公告)日：2008-05-08

申请号：PCT/US2005022659

申请日：2005-06-28

Applicant: UNIV CALIFORNIA ,  XIE YA-HONG

Inventor： XIE YA-HONG

IPC: B05D3/02

CPC classification number: B05D3/0218 ,  B05D1/185 ,  B05D1/208 ,  B05D3/0254 ,  B05D3/10 ,  B82Y30/00 ,  B82Y40/00 ,  G03F7/0002 ,  Y10T156/17

Abstract: A method of forming a self-assembled film with periodic nanometer dimension features (e.g., holes) on a substrate includes the steps of providing film precursors on the substrate, wherein the film precursors are maintained in an amorphous state. Where the film precursors are block copolymers, a heating member is provided. The substrate and the heating member are then moved relative to one another so as to raise the temperature of a portion of the film precursor on the substrate above its glass transition temperature. Relative movement between the substrate and heating member continues until a self-assembled crystalline film is formed over the surface of the substrate. In an alternative embodiment, a pH dispensing member is provided to dispense a pH adjusting agent onto the substrate that promotes self-assembly of a crystalline film.

Abstract translation: 在衬底上形成具有周期性纳米尺寸特征（例如，孔）的自组装膜的方法包括在衬底上提供膜前体的步骤，其中膜前体保持在非晶状态。 当膜前体是嵌段共聚物时，提供加热构件。 然后使衬底和加热构件相对于彼此移动，以便将衬底上的膜前体的一部分的温度升高到其玻璃化转变温度以上。 基板和加热部件之间的相对运动继续进行，直到在基板的表面上形成自组装的晶体膜。 在替代实施例中，提供pH分配构件以将pH调节剂分配到促进结晶膜自组装的衬底上。

公开(公告)号：WO2008005856A2

公开(公告)日：2008-01-10

申请号：PCT/US2007/072521

申请日：2007-06-29

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  XIE, Ya-Hong

Inventor： XIE, Ya-Hong

IPC: H01L29/40

CPC classification number: H01L29/66984 ,  Y10S977/935

Abstract: A spin injection device and spin transistor including a spin injection device. A spin injection device includes different semiconductor materials and a spin-polarizing ferromagnetic material there between. The semiconductor materials may have different crystalline structures, e.g., a first material can be polycrystalline or amorphous silicon, and a second material can be single crystalline silicon. Charge carriers are spin-polarized when the traverse the spin-polarizing ferromagnetic material and injected into the second semiconductor material. A Schottky barrier height between the first semiconductor and ferromagnetic materials is larger than a second Schottky barrier height between the ferromagnetic and second semiconductor materials. A spin injection device may be a source of a spin field effect transistor.

Abstract translation: 一种自旋注入装置和包括自旋注入装置的自旋晶体管。 自旋注入装置包括不同的半导体材料和其间的自旋极化铁磁材料。 半导体材料可以具有不同的结晶结构，例如，第一材料可以是多晶或非晶硅，第二材料可以是单晶硅。 当穿过自旋极化铁磁材料并注入到第二半导体材料中时，电荷载体是自旋极化的。 第一半导体和铁磁材料之间的肖特基势垒高度大于铁磁和第二半导体材料之间的第二肖特基势垒高度。 自旋注入装置可以是自旋场效应晶体管的源。

公开(公告)号：WO2007018495A2

公开(公告)日：2007-02-15

申请号：PCT/US2005/026364

申请日：2005-07-25

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  XIE, Ya-Hong ,  YOON, Tae-Sik

Inventor： XIE, Ya-Hong ,  YOON, Tae-Sik

IPC: H01L21/322

CPC classification number: H01L29/1054 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes depositing a strained silicon germanium layer on the substrate and irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent. The dislocation inducing agent may include ions, electrons, or other radiation source. Dislocations in the silicon germanium layer are located in one or more of the regions. The substrate and strained silicon germanium layer may then be subjected to an annealing process to transform the strained silicon germanium layer into a relaxed state. A top layer of strained silicon or silicon germanium may be deposited on the relaxed silicon germanium layer. Semiconductor-based devices may then be fabricated in the non-damaged regions of the strained silicon or silicon germanium layer. Threading dislocations are confined to damaged areas which may be transformed into SiO 2 isolation regions.

Abstract translation: 用于控制位于衬底上的硅锗缓冲层中的位错位置的方法包括在衬底上沉积应变硅锗层并且用位错诱导剂照射硅锗层的一个或多个区域 。 位错诱导剂可以包括离子，电子或其他辐射源。 硅锗层中的位错位于一个或多个区域中。 然后可以对衬底和应变硅锗层进行退火处理以将应变硅锗层转化为松弛状态。 应变硅或硅锗的顶层可以沉积在松弛硅锗层上。 然后可以在应变硅或硅锗层的未受损区域中制造基于半导体的器件。 线位错局限于可能转变成SiO 2隔离区的受损区域。

公开(公告)号：WO2007001296A2

公开(公告)日：2007-01-04

申请号：PCT/US2005/022672

申请日：2005-06-28

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  XIE, Ya-Hong

Inventor： XIE, Ya-Hong

IPC: H01L21/31

CPC classification number: H01L21/31604 ,  C23C16/045 ,  C23C16/45557 ,  C23C16/481 ,  H01L21/02271 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877

Abstract: A method of depositing conformal film into high aspect ratio spaces includes the step of forming a gradient of precursor gas inside the space (s) prior to deposition. The gradient may be formed, for example, by reducing the pressure within the deposition chamber or by partial evacuation of the deposition chamber. The temperature of the substrate is then briefly increased to preferentially deposit precursor material within the closed or "deep" portion of the high aspect ratio space. The process may be repeated for a number of cycles to completely fill the space (s). The process permits the filling of high aspect ratio spaces without any voids or keyholes that may adversely impact the performance of the resulting device.

Abstract translation: 将共形膜沉积成高纵横比空间的方法包括在沉积之前在空间内形成前体气体的梯度的步骤。 例如，可以通过降低沉积室内的压力或通过沉积室的部分排空来形成梯度。 然后短暂地增加衬底的温度以优先将前体材料沉积在封闭或“深层” 高纵横比空间的一部分。 该过程可以重复多次循环以完全填充空间。 该过程允许填充高纵横比空间，而不会有可能对所得设备的性能产生不利影响的空隙或锁眼。

公开(公告)号：WO2005059961A3

公开(公告)日：2005-10-27

申请号：PCT/US2004041566

申请日：2004-12-10

Applicant: UNIV CALIFORNIA ,  XIE YA-HONG

Inventor： XIE YA-HONG

IPC: H01L20060101 ,  H01L21/84 ,  H01L27/12 ,  H01L29/00 ,  H01L33/00

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/142 ,  H01L23/3736 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L29/78603 ,  H01L2223/6688 ,  H01L2924/0002 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal lager has regions with insulation filled channels or voids and a lager of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit lager. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip.

Abstract translation: 具有金属基板的集成电路层压板，用于与高性能混合信号集成电路应用。 金属基板提供了显着改进的串扰隔离，增强的散热和容易接近真正的低阻抗地。 在一个实施例中，金属加料器具有具有绝缘填充通道或空隙的区域，以及设置在金属基板和硅集成电路池之间的诸如未氧化多孔硅之类的绝缘体较大的区域。 层压板还具有安装到金属基底上的多个金属壁或沟槽，并且交互硅和绝缘层，从而将噪声敏感元件与芯片上产生噪声的元件隔离。 在另一个实施例中，层压板安装到柔性基座以限制芯片的弯曲。

公开(公告)号：WO2003044863A1

公开(公告)日：2003-05-30

申请号：PCT/US2002/037045

申请日：2002-11-19

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  TU, King-Ning ,  XIE, Ya-Hong ,  YEH, Chang-Ching

Inventor： TU, King-Ning ,  XIE, Ya-Hong ,  YEH, Chang-Ching

IPC: H01L29/00

CPC classification number: H01L21/76 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures : a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate (10) that allows for the subsequent formation of metallized posts (18) and metallized moats (16) in the porous regions; and a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats (16).

Abstract translation: 用于在用于射频应用的半导体衬底中制造高导电性区域的方法用于制造两种结构：第一结构包括遍及Si衬底10的整个厚度延伸的多孔Si硅区域，其允许随后形成金属化柱18和金属化护城河 16，并且第二结构包括从衬底的前部和/或后部蚀刻到Si衬底或某些其它半导体衬底中的交错的深V形槽或沟槽，其中这些V形沟槽和沟槽被填充 或涂覆金属以形成金属化护壁16。

公开(公告)号：WO2007001295A3

公开(公告)日：2009-04-30

申请号：PCT/US2005022661

申请日：2005-06-28

Applicant: UNIV CALIFORNIA ,  XIE YA-HONG

Inventor： XIE YA-HONG

IPC: H01L21/18 ,  H01L29/20 ,  H01L33/00 ,  H01S5/125 ,  H01S5/343

CPC classification number: H01S5/18341 ,  B82Y10/00 ,  B82Y20/00 ,  H01L33/0066 ,  H01L33/0087 ,  H01L33/20 ,  H01S5/0207 ,  H01S5/021 ,  H01S5/18308 ,  H01S5/18369 ,  H01S5/3224 ,  H01S5/341 ,  H01S5/3412 ,  Y10S977/784 ,  Y10S977/951

Abstract: A method of forming an optically active region on a silicon substrate includes the steps of epitaxially growing a silicon buffer layer on the silicon substrate and epitaxially growing a SiGe cladding layer having a plurality of arrays of quantum dots disposed therein, the quantum dots being formed from a compound semiconductor material having a lattice mismatch with the silicon buffer layer. The optically active region may be incorporated into devices such as light emitting diodes, laser diodes, and photodetectors.

Abstract translation: 在硅衬底上形成光学活性区域的方法包括以下步骤：在硅衬底上外延生长硅缓冲层并外延生长其中设置有多个量子点阵列的SiGe包层，量子点由 与硅缓冲层具有晶格失配的化合物半导体材料。 光学活性区域可以结合到诸如发光二极管，激光二极管和光电检测器的装置中。

公开(公告)号：WO2007018495A3

公开(公告)日：2007-12-13

申请号：PCT/US2005026364

申请日：2005-07-25

Applicant: UNIV CALIFORNIA ,  XIE YA-HONG ,  YOON TAE-SIK

Inventor： XIE YA-HONG ,  YOON TAE-SIK

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/76

CPC classification number: H01L29/1054 ,  B82Y10/00 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes depositing a strained silicon germanium layer on the substrate and irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent. The dislocation inducing agent may include ions, electrons, or other radiation source. Dislocations in the silicon germanium layer are located in one or more of the regions. The substrate and strained silicon germanium layer may then be subjected to an annealing process to transform the strained silicon germanium layer into a relaxed state. A top layer of strained silicon or silicon germanium may be deposited on the relaxed silicon germanium layer. Semiconductor-based devices may then be fabricated in the non-damaged regions of the strained silicon or silicon germanium layer. Threading dislocations are confined to damaged areas which may be transformed into SiO 2 isolation regions.

Abstract translation: 用于控制位于衬底上的硅锗缓冲层中的位错位置的方法包括在衬底上沉积应变硅锗层并用位错诱导剂照射硅锗层的一个或多个区域。 位错诱导剂可以包括离子，电子或其它辐射源。 硅锗层中的位错位于一个或多个区域中。 然后可以对衬底和应变硅锗层进行退火处理，以将应变硅锗层转变成松弛状态。 应变硅或硅锗的顶层可沉积在松散的硅锗层上。 然后可以在应变硅或硅锗层的未损坏区域中制造基于半导体的器件。 穿透位错限于可能转化为SiO 2隔离区的损坏区域。

公开(公告)号：WO2006113725A2

公开(公告)日：2006-10-26

申请号：PCT/US2006/014578

申请日：2006-04-18

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  XIE, Ya-hong ,  SHI, Bin

Inventor： XIE, Ya-hong ,  SHI, Bin

IPC: G02F1/03

CPC classification number: G02F1/218 ,  G02F2001/0157 ,  G02F2001/213

Abstract: A modulator for an optical transceiver is disclosed. The modulator has two quarter-wave stack mirrors composed of alternating dielectric layers with an optically absorbing layer sandwiched in between to form the vertical resonant cavity. The optically absorbing layer is made of semiconductor nanocrystals embedded in a dialectic material. The device is configured to operate near the saturation point of the absorption layer. By adjusting the biasing voltage across the absorption layer, the saturation threshold of the semiconductor nanocrystals is altered, resulting in the overall reflectivity of the resonant cavity to vary. The modulator is configured to be fabricated as the extension of the backend process of Si CMOS.

Abstract translation: 公开了一种用于光收发器的调制器。 调制器具有两个四分之一波长叠层反射镜，其由交替的电介质层组成，其间夹有光学吸收层以形成垂直谐振腔。 光学吸收层由嵌入辩证材料的半导体纳米晶体制成。 该装置被配置为在吸收层的饱和点附近操作。 通过调整吸收层两端的偏置电压，改变了半导体纳米晶体的饱和阈值，导致谐振腔的整体反射率发生变化。 调制器被配置为制造为Si CMOS的后端工艺的延伸。

公开(公告)号：WO2010096521A2

公开(公告)日：2010-08-26

申请号：PCT/US2010/024531

申请日：2010-02-18

Applicant: THE WATER INITIATIVE ,  FITZGERALD, Eugene, A. ,  XIE, Ya-Hong ,  LANGDO, Thomas ,  RENJILIAN, Richard ,  FOLEY, Brian, T. ,  THOMPSON, Carl, V.

Inventor： FITZGERALD, Eugene, A. ,  XIE, Ya-Hong ,  LANGDO, Thomas ,  RENJILIAN, Richard ,  FOLEY, Brian, T. ,  THOMPSON, Carl, V.

IPC: B01D35/00 ,  C02F1/28 ,  C02F103/02

CPC classification number: C02F1/004 ,  B01D27/146 ,  C02F1/003 ,  C02F1/008 ,  C02F1/281 ,  C02F1/283 ,  C02F1/68 ,  C02F1/688 ,  C02F2101/103 ,  Y02A20/156

Abstract: Water purification system comprising at least two filtration media sized with respect to each other to allow a first contaminate to be saturated first with a delay before a second contaminate is saturated.

Abstract translation: 水净化系统包括至少两个相对于彼此大小的过滤介质，以允许第一污染物在第二污染物饱和之前以延迟为先饱和。