公开(公告)号：WO2020173899A1

公开(公告)日：2020-09-03

申请号：PCT/EP2020/054828

申请日：2020-02-25

申请人： AUDI AG ,  ABB SCHWEIZ AG

发明人： TRAUB, Felix ,  SCHUDERER, Jürgen ,  MOHN, Fabian ,  GRADINGER, Thomas ,  LUI, Chunlei

IPC分类号： H01L23/473

摘要： An electric power converter device (1) comprises a first power semiconductor module (100) and a frame (20) for a closed cooler. The first power semiconductor module (100) includes a first base plate (30) having a first main side (32), a second main side (33) opposite the first main side and a lateral side surface (34) extending along a circumferential edge of the first base plate (30) and connecting the first and the second main side. The frame (20) is attached to the second main side (33) of the first base plate (20). The first base plate (30) has a first step (35A) on the second main side (33) along the circumferential edge of the first base plate (30) to form a first recess (35) along the circumferential edge of the first base plate (30), in which first recess (35) a first portion (21) of the frame (20) is received.

公开(公告)号：WO2018202615A1

公开(公告)日：2018-11-08

申请号：PCT/EP2018/061017

申请日：2018-04-30

申请人： ABB SCHWEIZ AG ,  AUDI AG

发明人： MOHN, Fabian

IPC分类号： H01L23/31 ,  H01L23/473 ,  H01L25/11

摘要： A power semiconductor module (10) comprises a substrate (12) with a metallization layer (18); at least one power semiconductor chip (14) bonded to the substrate (12); and a mold encapsulation (26) partially encapsulating the semiconductor chip (14) and the substrate 5 (12); wherein the mold encapsulation (26) comprises at least one window (36) exposing a terminal area (38, 40) of the metallization layer (18); and wherein a border part (34) of the mold encapsulation (26) between the window (36) and a border (28) of the substrate (12) has a height over the substrate smaller than a maximal height of a central part (32) of the mold encapsulation (26).10

公开(公告)号：WO2017157486A1

公开(公告)日：2017-09-21

申请号：PCT/EP2016/075970

申请日：2016-10-27

申请人： ABB SCHWEIZ AG ,  AUDI AG

发明人： LIU, Chunlei ,  MOHN, Fabian ,  BREM, Franziska

IPC分类号： H01L23/49 ,  H01L23/492

摘要： A semiconductor device (28) comprises a semiconductor element (10) with a power electrode area (16), a control electrode area (18) and an elevated control electrode structure (20) on one side, wherein the elevated control electrode structure (20) is interconnected with the control electrode area (18) and protrudes the power electrode area (16); and a grooved plate (30), which is bonded with a grooved side (34) to the power electrode area (16); wherein the grooved plate (30) has at least one groove (36) in the grooved side (34), in which at least a part of the control electrode structure (20) is accommodated, whereby the grooved plate (30) is sintered via a sintering preform (40) interpositioned between the grooved plate (30) and the semiconductor element (10) to the power electrode area (16), such that the sintering preform (40) covers the elevated control electrode structure (20).

摘要翻译： 半导体器件（28）包括在一侧具有功率电极区域（16），控制电极区域（18）和升高的控制电极结构（20）的半导体元件（10） 其中所述升高的控制电极结构（20）与所述控制电极区域（18）互连并且突出所述功率电极区域（16）; 和沟槽板（30），所述沟槽板（30）与沟槽侧（34）结合到所述功率电极区域（16）; 其特征在于，所述开槽板（30）在所述开槽侧（34）中具有至少一个凹槽（36），所述控制电极结构（20）的至少一部分容纳在所述凹槽中，其中所述开槽板（30） 在沟槽板（30）与半导体元件（10）之间插入功率电极区域（16）的烧结预型件（40），使得烧结预型件（40）覆盖升高的控制电极结构（20） p>

公开(公告)号：WO2017144599A1

公开(公告)日：2017-08-31

申请号：PCT/EP2017/054208

申请日：2017-02-23

申请人： ABB SCHWEIZ AG ,  AUDI AG

发明人： MOHN, Fabian ,  SCHUDERER, Jürgen ,  TRAUB, Felix

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/13 ,  H01L25/07 ,  H05K1/18 ,  H01L23/14

CPC分类号： H01L23/49822 ,  H01L23/13 ,  H01L23/142 ,  H01L23/5383 ,  H01L25/072 ,  H01L2224/0603 ,  H01L2224/40225 ,  H01L2224/48491 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0263 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10166 ,  H05K2201/10318

摘要： A power module (10) comprises at least one power semiconductor device (15a, 15b) with an electrical topcontact area (28b) on a top side; and a multi-layer circuit board (12) with multiple electrically conducting layers (16a, 16b, 18) which are separated by multiple electrically isolating layers (20), the electrically isolating layers (20) being laminated together with the electrically conducting layers (16a, 16b, 18); wherein the multi-layer circuit board (12) has at least one cavity (14), which is opened to a top side of the multi-layer circuit board (12), which cavity (14) reaches through at least two electrically conducting layers (16a, 16b, 18); wherein the power semiconductor device (15a, 15b) is attached with a bottom side to a bottom of the cavity (14); and wherein the power semiconductor device (15a, 15b) is electrically connected to a top side of the multi-layer circuit board (12) with a conducting member (26a, 26b) bonded to the top contact area (28b) and bonded to the top side of the multi-layer circuit board (12).

摘要翻译： 功率模块（10）包括至少一个功率半导体器件（15a，15b），所述至少一个功率半导体器件（15a，15b）在顶侧上具有电顶端接触区域（28b） 和具有由多个电隔离层（20）隔开的多个导电层（16a，16b，18）的多层电路板（12），所述电隔离层（20）与所述导电层 16a，16b，18）; 其中所述多层电路板（12）具有至少一个空腔（14），所述空腔（14）向所述多层电路板（12）的顶侧开放，所述空腔（14）通过至少两个导电层 （16a，16b，18）; 其中，所述功率半导体器件（15a，15b）的底侧连接到所述腔体（14）的底部; 并且其中所述功率半导体器件（15a，15b）通过结合到所述顶部接触区域（28b）的导电构件（26a，26b）电连接到所述多层电路板（12）的顶侧，并且结合到所述多层电路板 多层电路板（12）的顶侧。

公开(公告)号：WO2018096050A1

公开(公告)日：2018-05-31

申请号：PCT/EP2017/080248

申请日：2017-11-23

申请人： ABB SCHWEIZ AG ,  AUDI AG

发明人： MOHN, Fabian ,  LIU, Chunlei ,  SCHUDERER, Jürgen

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L21/56 ,  H01L25/07

摘要： A semi-manufactured power semiconductor module (10) comprises a substrate (12) for bonding at least one power semiconductor chip (22); a first leadframe (14) bonded to the substrate and providing power terminals (24); and a second leadframe (16) bonded to the substrate and providing auxiliary terminals (26); wherein the first leadframe (14) and/or the second leadframe (16) comprise an interlocking element (34) adapted for aligning the first leadframe (14) and the second leadframe (16) with respect to each other and/or with respect to a mold (40) for molding an encapsulation (38) around the substrate (12), the first leadframe (14) and the second leadframe (16).

公开(公告)号：WO2018202620A1

公开(公告)日：2018-11-08

申请号：PCT/EP2018/061027

申请日：2018-04-30

申请人： ABB SCHWEIZ AG ,  AUDI AG

发明人： MOHN, Fabian ,  TRAUB, Felix ,  SCHUDERER, Jürgen

IPC分类号： H01L25/07 ,  H01L23/498 ,  H01L23/538

摘要： A half-bridge module (10) comprises a substrate (12) with a base metallization layer (14) divided into a first DC conducting area (16), a second DC conducting area (20) and an AC conducting area (18); at least one first power semiconductor switch chip (22) bonded to the first DC conducting area (16) and electrically interconnected with the AC conducting area (18); at least one second power semiconductor switch chip (22) bonded to the AC conducting area (18) and electrically interconnected with the second DC conducting area (20); and a coaxial terminal arrangement (35) comprising at least one inner DC terminal (38), at least one first outer DC terminal (36) and at least one second outer DC terminal (40); wherein the at least one inner DC terminal (38), the at least first outer DC terminal (36) and the at least one second outer DC terminal (40) protrude from the module (10) and are arranged in a row, such that the at least one inner DC terminal (38) is coaxially arranged between the at least one first outer DC terminal (36) and the at least one second outer DC terminal (40); wherein the at least one inner DC terminal (38) is electrically connected to the second DC conducting area (20); wherein the at least one first outer DC terminal (36) and the at least one second outer DC terminal (40) are electrically connected to the first DC conducting area (16); and wherein the at least one first outer DC terminal (36) and the at least one second outer DC terminal (40) are electrically interconnected with an electrically conducting bridging element (52, 70) which is adapted for distributing at least a half of the load current between the at least one first outer DC terminal (36) and the at least one second outer DC terminal (40).

公开(公告)号：WO2016188909A1

公开(公告)日：2016-12-01

申请号：PCT/EP2016/061450

申请日：2016-05-20

申请人： ABB SCHWEIZ AG

发明人： TRAUB, Felix ,  MOHN, Fabian ,  SCHUDERER, Jürgen ,  KEARNEY, Daniel ,  KICIN, Slavo

IPC分类号： H01L23/538 ,  H01L23/64 ,  H01L25/07

CPC分类号： H01L23/5385 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/645 ,  H01L25/072 ,  H01L29/00 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2924/19107 ,  H01L2924/00014

摘要： The present invention relates to a power semiconductor module, comprising at least two power semiconductor devices, wherein the at least two power semiconductor devices comprise at least one power semiconductor transistor (22) and at least one power semiconductor diode (24), wherein at least a first substrate (26) is provided for carrying the power semiconductor transistor (22) in a first plane (44), the first plane lying parallel to the plane of the substrate (26), characterized in that the power semiconductor diode (24) is provided in a second plane (46), wherein the first plane (44) is positioned between the substrate (26) and the second plane (46) in a direction normal to the first plane (44) and wherein the first plane (44) is spaced apart from the second plane (46) in a direction normal to the first plane (44). The first plane (44) is spaced apart from the second plane (46) in a direction normal to the first plane (44), whereby the first substrate (26) is based on a direct bonded copper substrate and the first substrate (26) is a direct-bonded copper substrate for carrying the transistor (22), on which first substrate (26) a layer of a printed circuit board (PCB) is provided for carrying the diode (24). Alternatively, the first substrate (26) is a direct-bonded copper substrate for carrying the transistor (22), on which first substrate (26) a foil is provided for carrying the diode (24), wherein the foil comprises an electrically insulating main body and an electrically conductive structure provided thereon for carrying the diode (24). Such a power semiconductor module provides a low stray inductance and/or may be built easily.

摘要翻译： 本发明涉及功率半导体模块，其包括至少两个功率半导体器件，其中所述至少两个功率半导体器件包括至少一个功率半导体晶体管（22）和至少一个功率半导体二极管（24），其中至少 提供第一衬底（26），用于在第一平面（44）中承载功率半导体晶体管（22），该第一平面平行于衬底（26）的平面，其特征在于功率半导体二极管（24） 设置在第二平面（46）中，其中所述第一平面（44）在垂直于所述第一平面（44）的方向上位于所述基板（26）和所述第二平面（46）之间，并且其中所述第一平面 ）在垂直于第一平面（44）的方向上与第二平面（46）间隔开。 第一平面（44）在垂直于第一平面（44）的方向上与第二平面（46）间隔开，由此第一基底（26）基于直接键合的铜基底和第一基底（26）， 是用于承载晶体管（22）的直接接合的铜基板，其上设置有用于承载二极管（24）的印刷电路板（PCB）层的第一基板（26）。 或者，第一衬底（26）是用于承载晶体管（22）的直接键合铜衬底，第一衬底（26）上设置有用于承载二极管（24）的箔，其中箔包括电绝缘主体 主体和设置在其上的用于承载二极管（24）的导电结构。 这样的功率半导体模块提供了低杂散电感和/或可容易地构建。

公开(公告)号：WO2019197304A1

公开(公告)日：2019-10-17

申请号：PCT/EP2019/058748

申请日：2019-04-08

申请人： ABB SCHWEIZ AG

发明人： MOHN, Fabian ,  SOKOLOV, Alexey ,  LIU, Chunlei

IPC分类号： H01L21/60

摘要： A power semiconductor module (10) comprises a substrate (12) with a metallization layer (18); a power semiconductor chip (14) bonded to the metallization layer (18) of the substrate (12); and a metallic plate (24) bonded to the power semiconductor chip (14) opposite to the substrate (12). The metallic plate (24) has a border (36), which is structured in such a way that the metallic plate (24) has less metal material per area at the border (36) as compared to a central part (34) of the metallic plate (24).

公开(公告)号：WO2016184590A1

公开(公告)日：2016-11-24

申请号：PCT/EP2016/056140

申请日：2016-03-21

申请人： ABB SCHWEIZ AG

发明人： MOHN, Fabian ,  COMMIN, Paul

IPC分类号： H01L23/051

CPC分类号： H01L23/051 ,  H01L23/16 ,  H01L24/01

摘要： A semiconductor device (10) comprises two electrodes (12a, 12b) with opposite faces (14); a semiconductor wafer (16) sandwiched between the two electrodes (12a, 12b); an outer insulating ring (24) attached to the two electrodes (12a, 12b) and surrounding the semiconductor wafer (16); a middle insulating ring (40) inside the outer insulating ring (24) and surrounding the semiconductor wafer (16), whereby the middle insulating ring (40) is made of a plastics material; and an inner insulating ring (42) inside the middle insulating ring (40), whereby the inner insulating ring (42) is made of ceramics and/or glass material. Either the middle insulating ring (40) or the inner insulating ring (42) has a tongue (56) and the other thereof has a groove (58) such that the tongue (56) fits into the groove (58) for their rotational alignment. The middle insulating ring (40) and the inner insulating ring (42) have a radial opening (54) for receiving a gate connection (28) of the semiconductor device (10).

摘要翻译： 半导体器件（10）包括具有相对面（14）的两个电极（12a，12b）。 夹在两个电极（12a，12b）之间的半导体晶片（16）; 安装在所述两个电极（12a，12b）上并围绕所述半导体晶片（16）的外绝缘环（24）; 外绝缘环（24）内的中间绝缘环（40），并且包围半导体晶片（16），由此中间绝缘环（40）由塑料材料制成; 以及在所述中间绝缘环（40）内部的内绝缘环（42），由此所述内绝缘环（42）由陶瓷和/或玻璃材料制成。 中间绝缘环（40）或内绝缘环（42）均具有舌部（56），另一个具有凹槽（58），使得舌部（56）装配到凹槽（58）中用于它们的旋转对准 。 中间绝缘环（40）和内绝缘环（42）具有用于接收半导体器件（10）的栅极连接（28）的径向开口（54）。