公开(公告)号：WO2016187038A1

公开(公告)日：2016-11-24

申请号：PCT/US2016/032451

申请日：2016-05-13

Applicant: ATOMERA INCORPORATED

Inventor： MEARS, Robert, J. ,  TAKEUCHI, Hideki

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/15

CPC classification number: H01L29/157 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0638 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/152 ,  H01L29/155 ,  H01L29/158 ,  H01L29/42384 ,  H01L29/66537 ,  H01L29/7833

Abstract: A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice.

Abstract translation: 半导体器件可以包括半导体衬底和具有第一工作电压的第一晶体管。 每个第一晶体管可以包括半导体衬底中的第一通道和第一穿通阻挡层（PTS），并且第一PTS层可以处于第一通道下方的第一深度。 半导体器件还可以包括具有高于第一工作电压的第二工作电压的第二晶体管。 每个第二晶体管可以包括半导体衬底中的第二沟道和第二PTS层，并且第二PTS层可以处于比第一深度大的第二沟道的第二深度。 此外，第一通道可以包括第一超晶格，并且第二通道可以包括第二超晶格。

公开(公告)号：WO2021011629A1

公开(公告)日：2021-01-21

申请号：PCT/US2020/042103

申请日：2020-07-15

Applicant: ATOMERA INCORPORATED

Inventor： BURTON, Richard ,  HYTHA, Marek ,  MEARS, Robert, J.

IPC: H01L29/15 ,  H01L29/93 ,  H01L29/78 ,  H01L29/808

Abstract: A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction region, and a second contact coupled to the substrate to define a varactor.

公开(公告)号：WO2018031522A1

公开(公告)日：2018-02-15

申请号：PCT/US2017/045853

申请日：2017-08-08

Applicant: ATOMERA INCORPORATED

Inventor： MEARS, Robert, J. ,  TAKEUCHI, Hideki ,  HYTHA, Marek

IPC: H01L29/88 ,  H01L21/329 ,  H01L29/15

Abstract: A semiconductor device includes at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD includes a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer, the first barrier layer including a superlattice. The superlattice includes stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD further includes an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.

Abstract translation: 半导体器件包括至少一个双势垒谐振隧穿二极管（DBRTD）。 所述至少一个DBRTD包括第一掺杂半导体层和在所述第一掺杂半导体层上的第一阻挡层，所述第一阻挡层包括超晶格。 超晶格包括堆叠的层组，每组层包括限定基础半导体部分的多个堆叠的基础半导体单层和限制在相邻基础半导体部分的晶格内的至少一个非半导体单层。 所述至少一个DBRTD进一步包括在第一阻挡层上的本征半导体层，在本征半导体层上的第二阻挡层和在第二超晶格层上的第二掺杂半导体层。

公开(公告)号：WO2022245889A1

公开(公告)日：2022-11-24

申请号：PCT/US2022/029752

申请日：2022-05-18

Applicant: ATOMERA INCORPORATED

Inventor： MEARS, Robert, J. ,  TAKEUCHI, Hideki

IPC: H01L29/08 ,  H01L29/15 ,  H01L21/336 ,  H01L29/775 ,  H01L29/423 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/165

Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and including a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

公开(公告)号：WO2019036572A1

公开(公告)日：2019-02-21

申请号：PCT/US2018/046854

申请日：2018-08-17

Applicant: ATOMERA INCORPORATED

Inventor： STEPHENSON, Robert, John ,  KREPS, Scott A. ,  MEARS, Robert, J. ,  RAO, Kalipatnam, Vivek

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/10 ,  H01L29/15

Abstract: A semiconductor device may include a semiconductor substrate and first and second spaced apart shallow trench isolation (STI) regions therein, and a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first semiconductor stringer including a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and a gate above the superlattice.

公开(公告)号：WO2016196600A1

公开(公告)日：2016-12-08

申请号：PCT/US2016/035223

申请日：2016-06-01

Applicant: ATOMERA INCORPORATED

Inventor： MEARS, Robert, J. ,  CODY, Nyles ,  STEPHENSON, Robert, John

IPC: H01L29/15

CPC classification number: H01L21/02507 ,  H01L21/0245 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/151 ,  H01L29/152

Abstract: A method for processing a semiconductor wafer in a single wafer processing chamber may include heating the single wafer processing chamber to a temperature in a range of 650-700°C, and forming at least one superlattice on the semiconductor wafer within the heated single wafer processing chamber by depositing silicon and oxygen to form a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Depositing the oxygen may include depositing the oxygen using an N 2 O gas flow.

Abstract translation: 在单个晶片处理室中处理半导体晶片的方法可以包括将单晶片处理室加热到650-700℃的温度，并且在加热的单晶片处理中在半导体晶片上形成至少一个超晶格 通过沉积硅和氧来形成多个堆叠的层组。 每组层可以包括限定基硅部分的多个堆叠的基底硅单层和限制在相邻基硅部分的晶格内的至少一个氧单层。 沉积氧气可以包括使用N 2 O气流沉积氧气。