公开(公告)号：WO2014120693A1

公开(公告)日：2014-08-07

申请号：PCT/US2014/013463

申请日：2014-01-29

Applicant: VARIAN MEDICAL SYSTEMS, INC.

Inventor： BANDIS, Steven Douglas

IPC: H01M2/10 ,  H01M2/08 ,  G01T1/161

CPC classification number: H01M2/1094 ,  A61B6/4283 ,  A61B6/4405 ,  A61B6/4411 ,  A61B6/56 ,  B29L2031/7146 ,  G06F1/1635 ,  H01L27/14618 ,  H01M2/0202 ,  H01M2/0207 ,  H01M2/08 ,  H01M2/1022 ,  H01M2/1066 ,  H01M2220/30 ,  Y10S224/902 ,  Y10S257/924

Abstract: An electronic device employs a seal member to seal a battery pack to a housing member to prevent contaminants from entering into a battery bay. The electronic device includes a housing member having an exterior surface a portion of which defines a recess, an electronic assembly contained inside the housing member, and an battery pack received in the recess in the exterior surface of the housing member and electrically connected to the electronic assembly inside the housing member. The seal member engages the battery pack and the housing member along an outer circumference of the battery pack and an inner circumference of the recess such that the seal member seals the gap between the outer circumference of the battery pack and the inner circumference of the recess, thereby preventing contaminants from an external environment from entering into an interior of the recess through the gap.

Abstract translation: 电子装置采用密封构件将电池组密封到外壳构件以防止污染物进入电池槽。 电子设备包括外壳部件，外壳部分的一部分限定凹部，容纳在壳体部件内的电子组件以及容纳在壳体部件的外表面中的凹部中的电池组件，并电连接到电子部件 组装在壳体构件内。 密封构件沿着电池组的外周和凹部的内周接合电池组和壳体构件，使得密封构件密封电池组的外周与凹部的内周之间的间隙， 从而防止来自外部环境的污染物通过间隙进入凹部的内部。

公开(公告)号：WO2004038916A3

公开(公告)日：2004-08-12

申请号：PCT/EP0312399

申请日：2003-09-18

Applicant: IBM ,  IBM FRANCE

Inventor： CHINTHAKINDI ANIL K ,  GROVES ROBERT A ,  STEIN KENNETH J ,  SUBBANNA SESHADRI ,  VOLANT RICHARD P

IPC: B81B7/00 ,  B81C1/00 ,  H01G5/011 ,  H01G5/18 ,  H03J3/18 ,  B81B3/00 ,  H01G5/16

CPC classification number: H01G5/18 ,  B81B2201/01 ,  H01G5/011 ,  Y10S257/924

Abstract: A three-dimensional micro-electromechanical (MEM) varactor is described wherein a movable beam (50) and fixed electrodes (51) are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the "chip side" while the fixed bottom electrode is fabricated on a separated substrate "carrier side". Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and "flipped over", aligned and joined to the "carrier" substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.

Abstract translation: 描述了三维微机电（MEM）变容二极管，其中可移动光束（50）和固定电极（51）分别制造在彼此耦合的分离的基板上。 具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。 在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。 梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。 由于所涉及的驱动力恒定，可以获得大的电容调谐范围。 该装置的三维方面具有较大的表面积。 当提供大的纵横比特征时，可以使用较低的致动电压。 在制造时，MEMS器件被完全封装，不需要额外的器件封装。 此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。

公开(公告)号：WO0219293A2

公开(公告)日：2002-03-07

申请号：PCT/US0126985

申请日：2001-08-30

Applicant: UT BATTELLE LLC

Inventor： SMITH STEPHEN F ,  TURNER GARY W ,  WINTENBERG ALAN L ,  EMERY MICHAEL STEVEN

IPC: G01D21/00 ,  G08C17/02 ,  G08C

CPC classification number: G01D21/00 ,  G08C17/02 ,  Y10S257/924

Abstract: A fully integrated wireless spread-spectrum sensor incorporating all elements of an "intelligent" sensor on a single circuit chip is capable of telemetering data to a receiver. Synchronous control of all elements of the chip provides low-cost, low-noise, and highly robust data transmission, in turn enabling the use of low-cost monolithic receivers.

Abstract translation: 在单个电路芯片上集成了“智能”传感器的所有元件的完全集成的无线扩频传感器能够将数据遥测到接收机。 芯片的所有元件的同步控制提供低成本，低噪声和高度鲁棒的数据传输，从而能够使用低成本的单片接收器。

公开(公告)号：WO2004102618A3

公开(公告)日：2005-03-03

申请号：PCT/US2004013010

申请日：2004-05-12

Applicant: SOLICORE INC ,  WENSLEY C GLEN ,  GUSTAFSON SCOTT ,  NELSON CRAIG R

Inventor： WENSLEY C GLEN ,  GUSTAFSON SCOTT ,  NELSON CRAIG R

IPC: H01L20060101 ,  H01L23/02 ,  H01M2/00 ,  H01M2/08 ,  H01M2/16 ,  H01M4/40 ,  H01M4/62 ,  H01M6/18 ,  H01M6/40 ,  H01M10/04 ,  H01M10/052 ,  H01M10/0525 ,  H01M10/0565 ,  H01M10/0585 ,  H01M10/36 ,  H01M10/42 ,  B32B31/00 ,  H01M10/40

CPC classification number: H01M2/08 ,  H01M2/0207 ,  H01M2/0275 ,  H01M2/166 ,  H01M6/181 ,  H01M6/40 ,  H01M10/044 ,  H01M10/052 ,  H01M10/0525 ,  H01M10/0565 ,  H01M10/0585 ,  H01M10/425 ,  H01M2300/0082 ,  H01M2300/0091 ,  Y10S257/924 ,  Y10T29/49108 ,  Y10T29/49112

Abstract: An IC card includes at least one plastic layer (915), a battery (865) and at least one electronic device (980) embedded in the plastic layer (915). The battery (865) is electrically connected to the electronic device (980) for providing power to the device (980). The battery (865) includes an anode, a cathode, and at least one polymer matrix electrolyte (PME) separator disposed between the anode and the cathode. The PME separator includes a polyimide, at least one lithium salt and at least one solvent all intermixed. The PME is substantially optically clear and stable against high temperature and pressure, such as processing conditions typically used in hot lamination processing or injection molding.

Abstract translation: IC卡包括嵌入塑料层（915）中的至少一个塑料层（915），电池（865）和至少一个电子装置（980）。 电池（865）电连接到用于向设备（980）供电的电子设备（980）。 电池（865）包括阳极，阴极和设置在阳极和阴极之间的至少一个聚合物基质电解质（PME）隔离物。 PME分离器包括聚酰亚胺，至少一种锂盐和至少一种全部混合的溶剂。 PME在高温和高压下基本上光学透明且稳定，例如通常用于热层压加工或注射成型的加工条件。

公开(公告)号：WO2004077508A3

公开(公告)日：2005-01-27

申请号：PCT/US2004004676

申请日：2004-02-17

Applicant: ADVANCED INTERCONNECT TECH LTD ,  JUSKEY FRANK J ,  LAU DANIEL K ,  THOMPSON LAWRENCE R

Inventor： JUSKEY FRANK J ,  LAU DANIEL K ,  THOMPSON LAWRENCE R

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/48

CPC classification number: H01L23/3107 ,  H01L23/49541 ,  H01L23/49589 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/85207 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  Y10S257/924 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected to the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12) , passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).

Abstract translation: 半导体器件封装（10）包括电连接到公共引线框架（17）的半导体器件（管芯）（12）和无源器件（14）。 引线框架（17）由冲压和/或蚀刻的金属结构形成，并且包括多个导电引线（16）和多个插入件（20）。 无源器件（14）电连接到插入件（20），并且管芯（12）上的I / O焊盘（22）电连接到引线（16）。 模具（12），无源器件（14）和引线框架（17）被封装在形成封装主体（30）的模制化合物（28）中。 引线（16）的底表面（38）在封装（10）的底面（34）处露出。

公开(公告)号：WO2002089207A2

公开(公告)日：2002-11-07

申请号：PCT/US2002/012088

申请日：2002-04-19

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  TANG, John ,  TOWLE, Steven

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/24 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19106 ,  H01L2924/3011 ,  Y10S257/924

Abstract: A low cost packaging technique for microelectronic circuit chips fixes a die within an opening in a package core. At least one metallic build up layer is then formed on the die/core assembly and a grid array interposer unit is laminated to the build up layer. The grid array interposer unit can then be mounted within an external circuite using any of a plurality of mounting technologies (e.g., ball grid array (BGA), land grid array (LGA), pin grid array (PGA), surface mount technology (SMT), and/or others). In one embodiment, a single build up layer is formed on the die/core cassembly before lamination of the interposer.

Abstract translation: 用于微电子电路芯片的低成本封装技术将芯片固定在封装芯的开口内。 然后在模具/芯组件上形成至少一个金属堆积层，并且将栅格阵列插入单元层叠到堆积层上。 然后可以使用多种安装技术（例如，球栅阵列（BGA），平面栅格阵列（LGA），针阵列阵列（PGA），表面贴装技术（SMT）等）中的任何一种将栅格阵列插入单元安装在外部环路内 ）和/或其他）。 在一个实施例中，在层压插入件之前，在芯/芯组件上形成单个堆积层。

公开(公告)号：WO02056367A1

公开(公告)日：2002-07-18

申请号：PCT/AU2002/000008

申请日：2002-01-08

IPC: H01L23/02 ,  B29C33/38 ,  B29C33/40 ,  B29C35/08 ,  B29C43/36 ,  B29C45/12 ,  B81B7/00 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/8238 ,  H01L23/10 ,  H01L23/12 ,  H01L21/822 ,  H01L23/04

CPC classification number: B81C1/00333 ,  B29C33/0022 ,  B29C33/3842 ,  B29C43/36 ,  B29C2035/0822 ,  B29C2043/503 ,  B81C2203/0109 ,  B81C2203/0127 ,  H01L21/50 ,  H01L2224/48463 ,  H01L2924/1461 ,  Y10S257/924 ,  H01L2924/00

Abstract: The invention is a method of applying an array (134) of caps to a wafer (144) of semiconductor material which includes a plurality of microfabricated devices (146). The method includes applying the array (134) of first caps substantially simultaneously to one side of the wafer (144), bonding the array (134) of caps to the wafer(144) and then separating the wafer into individual packages (148).

Abstract translation: 本发明是一种将帽的阵列（134）应用于包括多个微加工装置（146）的半导体材料的晶片（144）的方法。 该方法包括将第一盖的阵列（134）基本上同时施加到晶片（144）的一侧，将盖的阵列（134）接合到晶片（144），然后将晶片分离成单个封装（148）。

公开(公告)号：WO2005058749A1

公开(公告)日：2005-06-30

申请号：PCT/US2004/041549

申请日：2004-12-09

Applicant: ANALOG DEVICES, INC. ,  ALIE, Susan, A. ,  WACHTMANN, Bruce, K. ,  JUDY, Michael ,  KNEEDLER, David

Inventor： ALIE, Susan, A. ,  WACHTMANN, Bruce, K. ,  JUDY, Michael ,  KNEEDLER, David

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81C2203/019 ,  H01L2224/16225 ,  Y10S257/924

Abstract: An apparatus has first and second wafers, and a conductive rim between the first and second wafers. The conductive rim electrically and mechanically connects the first and second wafers. In addition, the conductive rim and second wafer at least in part seal an area on the surface of the first wafer.

Abstract translation: 一种装置具有第一和第二晶片，以及在第一和第二晶片之间的导电边缘。 导电边缘电和机械地连接第一和第二晶片。 此外，导电边缘和第二晶片至少部分地密封第一晶片的表面上的区域。

公开(公告)号：WO2003100858A2

公开(公告)日：2003-12-04

申请号：PCT/US2003/015972

申请日：2003-05-21

Applicant: INTEL CORPORATION

Inventor： SEARLS, Damion ,  ROTH, Weston ,  JACKSON, James

IPC: H01L23/64

CPC classification number: H01L24/81 ,  H01L23/642 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/145 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10S257/924 ,  Y10S438/957

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract translation: 封装高性能微电子器件（例如处理器）的系统响应元件瞬变。 在一个实施例中，该系统包括设置在Vcc电凸起和Vss电凸起之间的去耦电容器。 去耦电容器具有Vcc和Vss端子。 Vcc和Vss端子与Vcc电气凸块和Vss电气凸块共享电气垫。 创建一个简单的电流循环，可以改善系统的功率传递。

公开(公告)号：WO01048820A1

公开(公告)日：2001-07-05

申请号：PCT/JP1999/007257

申请日：1999-12-24

IPC: H01L23/48 ,  H01L23/50 ,  H01L23/64 ,  H01L25/00 ,  H01L23/36 ,  H01L27/04

CPC classification number: H01L23/642 ,  H01L23/481 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor bare chip and a board member with a thin-film structure capacitor. The semiconductor bare chip has a power supply terminal and a grounding terminal on the back thereof, and mounted on a circuit board by flip-chip bonding. The board member comprises a board and a thin-film structure capacitor provided on the board. The capacitor has terminals corresponding to the power supply terminal and grounding terminal of the semiconductor bare chip thereon. The side of the board member where the capacitor is provided is bonded to the back of the semiconductor bare chip. The terminals of the capacitor are electrically connected to the power supply terminal and grounding terminal of the semiconductor bare chip.

Abstract translation: 半导体器件包括半导体裸芯片和具有薄膜结构电容器的板构件。 半导体裸芯片的背面具有电源端子和接地端子，并且通过倒装芯片接合而安装在电路板上。 板构件包括设置在板上的板和薄膜结构电容器。 电容器具有对应于其上的半导体裸芯片的电源端子和接地端子的端子。 提供电容器的电路板部件的一侧与半导体裸芯片的背面接合。 电容器的端子电连接到半导体裸芯片的电源端子和接地端子。