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    RESISTIVE RANDOM-ACCESS MEMORY INCLUDING TUNNEL SOURCE ACCESS TRANSISTOR
    3.
    发明申请
    RESISTIVE RANDOM-ACCESS MEMORY INCLUDING TUNNEL SOURCE ACCESS TRANSISTOR 审中-公开

    公开(公告)号：WO2019005113A1

    公开(公告)日：2019-01-03

    申请号：PCT/US2017/040321

    申请日：2017-06-30

    Applicant: INTEL CORPORATION

    Inventor： MORRIS, Daniel H. ,  AVCI, Uygar E. ,  YOUNG, Ian A.

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2418

    Abstract: Techniques are disclosed for forming resistive random-access memory (RRAM) including a tunnel source access transistor, such as a tunnel source MOSFET. The use of a tunnel source access transistor includes integrating a tunnel diode on the bitcell transistor's source terminal using epitaxial growth. Accordingly, such RRAM bitcells are referred to herein as having a 1T(D)-1R configuration. As can be understood based on this disclosure, the tunnel diode's resistance is asymmetric with respect to RRAM write voltage. Thus, the tunnel diode optimizes array operations for the 1T(D)-1R bitcells described herein, enabling both control of current compliance in the SET direction and maximization of current in the RESET direction from the same RRAM bitcell. The 1T(D)-1R architecture is compatible with a multitude of RRAM device structures and transistor types, such as NMOS and PMOS configurations. Further, the tunnel diode can be integrated in a MOSFET access transistor without increasing cell layout area.

    APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS
    4.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS 审中-公开
    使用隧道场效应晶体管的DENSE电路的装置，方法和系统

    公开(公告)号：WO2016099718A1

    公开(公告)日：2016-06-23

    申请号：PCT/US2015/060180

    申请日：2015-11-11

    Applicant: INTEL CORPORATION

    Inventor： MORRIS, Daniel H. ,  AVCI, Uygar E. ,  RIOS, Rafael ,  YOUNG, Ian A.

    IPC: H03K19/0185

    CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C11/412 ,  H01L27/1104 ,  H03K3/356104

    Abstract: Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.

    Abstract translation: 实施例包括用于移位电压电平的电路的装置，方法和系统。 电路可以包括第一反相器，其包括耦合以传递低电压信号的第一晶体管和耦合以接收低电压信号的第二反相器。 电路还可以包括第二晶体管，其被耦合以从第二反相器接收低电压信号，以用作反馈装置并产生高电压信号。 在实施例中，第一晶体管不对称地导通，以防止高电压信号到低电压域的交叉。 还描述了低电压存储器阵列。 在实施例中，用于移位电压电平的电路可以有助于包括低电压域的低电压存储器阵列和高电压域的逻辑分量的逻辑组件之间的通信。 还可以描述另外的实施例。

    ASYMMETRICAL WRITE DRIVER FOR RESISTIVE MEMORY
    7.
    发明申请
    ASYMMETRICAL WRITE DRIVER FOR RESISTIVE MEMORY 审中-公开
    非对称写入驱动器用于抵抗记忆

    公开(公告)号：WO2017204957A1

    公开(公告)日：2017-11-30

    申请号：PCT/US2017/028652

    申请日：2017-04-20

    Applicant: INTEL CORPORATION

    Inventor： LIU, Huichu ,  MORRIS, Daniel H. ,  MANIPATRUNI, Sasikanth ,  VAIDYANATHAN, Kaushik ,  YOUNG, Ian A. ,  KARNIK, Tanay

    IPC: G11C13/00 ,  G11C11/16

    Abstract: An apparatus is provided which comprises: a select line; a select transistor coupled to a resistive memory element and to the select line; a word-line coupled to a gate terminal of the select transistor; and a current mirror operable to be coupled to the select line during a first mode and to be de-coupled during a second mode.

    Abstract translation: 提供了一种设备，其包括：选择线; 耦合到电阻存储器元件和选择线的选择晶体管; 耦合到所述选择晶体管的栅极端子的字线; 以及电流镜，可操作以在第一模式期间耦合到选择线并在第二模式期间解耦合。

    TRANSISTOR THRESHOLD VOLTAGE VARIATION OPTIMIZATION
    8.
    发明申请
    TRANSISTOR THRESHOLD VOLTAGE VARIATION OPTIMIZATION 审中-公开
    晶体管阈值电压变化优化

    公开(公告)号：WO2017171860A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2016/025663

    申请日：2016-04-01

    Applicant: INTEL CORPORATION

    Inventor： MORRIS, Daniel H. ,  AVCI, Uygar E. ,  YOUNG, Ian A.

    IPC: H01L29/78 ,  H01L27/04

    CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

    Abstract: One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors.

    Abstract translation: 一个实施例提供了一种装置。 该装置包括第一晶体管和第二晶体管。 第一晶体管包括第一漏极，通过第一沟道耦合到第一漏极的第一源极以及包括多个层的第一栅极堆叠。 第二晶体管包括第二漏极，通过第二沟道耦合到第二漏极的第二源极以及包括多个层的第二栅极堆叠。 每个栅极叠层包括功函数材料层以优化晶体管之间的阈值电压变化。

    POLARIZATION GATE STACK SRAM
    9.
    发明申请
    POLARIZATION GATE STACK SRAM 审中-公开

    公开(公告)号：WO2017171846A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2016/025606

    申请日：2016-04-01

    Applicant: INTEL CORPORATION

    Inventor： MORRIS, Daniel H. ,  AVCI, Uygar E. ,  YOUNG, Ian A.

    IPC: G11C11/412 ,  G11C11/413

    Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

    Abstract translation: 一个实施例提供了一种装置。 该装置包括：第一反相器，包括第一上拉晶体管和第一下拉晶体管; 第二反相器，交叉耦合到所述第一反相器，所述第二反相器包括第二上拉晶体管和第二下拉晶体管; 耦合到第一反相器的第一存取晶体管; 以及耦合到第二反相器的第二存取晶体管。 每个逆变器的一个晶体管的栅电极包括偏振层。

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