公开(公告)号：WO2015142357A1

公开(公告)日：2015-09-24

申请号：PCT/US2014/031486

申请日：2014-03-21

Applicant: INTEL CORPORATION ,  GLASS, Glenn A. ,  MURTHY, Anand S. ,  GHANI, Tahir ,  PANG, Ying ,  MISTKAWI, Nabil, G.

Inventor： GLASS, Glenn A. ,  MURTHY, Anand S. ,  GHANI, Tahir ,  PANG, Ying ,  MISTKAWI, Nabil, G.

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/94 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm -3 .

Abstract translation: 公开了用于改善锗（Ge）富集的p-MOS源极/漏极触点的集成的技术，例如降低接触电阻。 这些技术包括将p型富锗层直接沉积在接触沟槽位置的硅（Si）表面上，因为Si表面有利于沉积高质量的导电富Ge材料。 在一个示例性方法中，在去除先前沉积在源极/漏极位置中的牺牲硅锗（SiGe）层之后，在源/漏接触沟槽位置中的富Si层沉积在Si衬底的表面上。 在另一示例性方法中，富集层沉积在接触沟槽位置中的Si包覆层上，其中Si包覆层沉积在功能性p型SiGe层上。 在一些情况下，富锗层包含至少50％的Ge（并且可以含有锡（Sn）和/或Si），并且是以高于1E20cm-3的掺杂的硼（B）。

公开(公告)号：WO2016209220A1

公开(公告)日：2016-12-29

申请号：PCT/US2015/037344

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： GLASS, Glenn A. ,  PANG, Ying ,  MISTKAWI, Nabil G. ,  MURTHY, Anand S. ,  GHANI, Tahir ,  CHAO, Huang-Lin

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/20 ,  H01L29/6681

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.

Abstract translation: 公开了用于定制鳍式晶体管器件以提供不同范围的通道配置和/或材料系统以及在同一集成电路管芯内的技术。 牺牲翅片通过湿和/或干蚀刻化学物质去除，其被配置为提供非面的沟槽底部，并且没有或以其它方式低离子损伤。 然后用期望的半导体材料填充沟槽。 具有低离子损伤和非刻面形态的沟槽底部促进了衬底和替换材料之间的无缺陷或低缺陷界面。 在一个实施例中，第一组牺牲硅散热片中的每一个被凹入并用p型材料代替，并且第二组牺牲散热片中的每一个凹进并用n型材料代替。 另一个实施例可以包括天然散热片（例如Si）和替代翅片（例如，SiGe）的组合。 另一实施例可以包括全部相同配置的替换散热片。

公开(公告)号：WO2016209219A1

公开(公告)日：2016-12-29

申请号：PCT/US2015/037326

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： GLASS, Glenn A. ,  PANG, Ying ,  MURTHY, Anand S. ,  GHANI, Tahir ,  JAMBUNATHAN, Karthik

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/408 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.

Abstract translation: 公开了通过使用亚翅片钝化层来减少鳍状晶体管的截止状态泄漏的技术。 在一些情况下，这些技术包括在体硅衬底中形成牺牲翅片并沉积和平坦化浅沟槽隔离（STI）材料，用替换材料（例如SiGe或III-V材料）去除和替换牺牲硅散热片，去除 STI材料的至少一部分以暴露替代翅片的副鳍片区域，向暴露的子鳍片施加钝化层/处理剂/试剂，以及重新沉积和平坦化另外的STI材料。 然后可以执行标准晶体管形成工艺以完成晶体管器件。 这些技术通常提供为在基于STI的沟槽中生长的结构添加任意钝化层的能力。 钝化层抑制子鳍源极到漏极（和漏极到源极）的电流泄漏。