公开(公告)号：WO2014085267A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/071533

申请日：2013-11-22

Applicant: INTEL CORPORATION ,  VERGIS, George ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  CHANG, Ge

Inventor： VERGIS, George ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  CHANG, Ge

IPC: G11C11/40

CPC classification number: G11C11/4074 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F13/1663 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/06 ,  G11C11/408 ,  Y10T29/41

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

Abstract translation: 用于为存储器件的多个芯片提供终端的技术和机制。 在一个实施例中，存储器件是集成电路（IC）封装，其包括命令和地址总线以及与其耦合的多个存储器芯片。 在多个存储器芯片中，只有第一存储器芯片可操作以选择性地提供对命令和地址总线的终止。 在多个存储器芯片的各个片上终端控制电路中，仅第一存储器芯片的片上终端控制电路经由任何终端控制信号线耦合到任何输入/输出（I / O）触点 IC封装。 在另一个实施例中，多个存储器芯片彼此串联配置，并且其中第一存储器芯片位于该系列的一端

公开(公告)号：WO2013095518A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066891

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S. ,  RUFF, Klaus J. ,  VERGIS, George ,  SAH, Suneeta

Inventor： BAINS, Kuljit S. ,  RUFF, Klaus J. ,  VERGIS, George ,  SAH, Suneeta

IPC: G06F12/00 ,  G06F11/10 ,  G06F13/14

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Abstract translation: 通过将数据通过地址总线传送到连接到数据总线的设备来读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。 寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。 主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。 然后主机处理器从存储器件的寄存器读取信息。

公开(公告)号：WO2012078397A2

公开(公告)日：2012-06-14

申请号：PCT/US2011/062315

申请日：2011-11-29

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S.

Inventor： BAINS, Kuljit S.

IPC: G06F11/08 ,  G11C29/42

CPC classification number: H03M13/09 ,  G06F11/1052 ,  H03M13/6505

Abstract: On the fly enabling and disabling of error detection for memory access transactions on a transaction basis is provided. Dynamic enabling and disabling of error detection for memory access transactions can also be applied for multiple transactions. Control logic associated with the memory device determines whether to apply error detection, and selectively enables error detection in the memory access transaction. The selective enabling of error detection in a memory access transaction can apply to either reads or writes.

Abstract translation: 提供了在事务基础上快速启用和禁用内存访问事务的错误检测。 动态启用和禁用内存访问事务的错误检测也可以应用于多个事务。 与存储器件相关联的控制逻辑确定是否应用错误检测，并且选择性地启用存储器访问事务中的错误检测。 存储器访问事务中的错误检测的选择性启用可以应用于读取或写入。

公开(公告)号：WO2010039625A2

公开(公告)日：2010-04-08

申请号：PCT/US2009/058531

申请日：2009-09-28

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S. ,  HALBERT, John

Inventor： BAINS, Kuljit S. ,  HALBERT, John

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4063 ,  G11C7/00

CPC classification number: G11C8/12 ,  G11C7/1021 ,  G11C7/1045 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

Abstract translation: 本发明的实施例通常针对用于可变设备宽度和可缩放预取和页面大小的公共存储器设备的系统，方法和设备。 在一些实施例中，公共存储器设备（诸如DRAM）可以以包括例如x4模式，x8模式和x16模式的多种模式中的任何模式进行操作。 由DRAM提供的页面大小可以根据DRAM的模式而变化。 在一些实施例中，由DRAM预取的数据量也取决于DRAM的模式而变化。

公开(公告)号：WO2014085268A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/071534

申请日：2013-11-22

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S.

Inventor： BAINS, Kuljit S.

IPC: G11C11/4063 ,  G11C11/406

CPC classification number: G11C11/4074 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F13/1663 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/06 ,  G11C11/408 ,  Y10T29/41

Abstract: Techniques and mechanisms for determining a timing of a command to access a memory device resource. In an embodiment, a multi-cycle command which is exchanged from a memory controller to a memory device, wherein the multi-cycle command indicates an access to a bank of the memory device. Timing of the one or more other commands is controlled, based on the multi-cycle command, to enforce a time delay parameter which describes an operational constraint of the memory device. In another embodiment, timing of one or more commands is determined with reference to a beginning of a last cycle of a multi-cycle command.

Abstract translation: 用于确定访问存储器设备资源的命令的定时的技术和机制。 在一个实施例中，从存储器控制器交换到存储器件的多循环命令，其中多周期命令指示对存储器件的存储体的访问。 基于多周期命令来控制一个或多个其他命令的定时，以强制描述存储器件的操作约束的时间延迟参数。 在另一个实施例中，参考多循环命令的最后一个循环的开始来确定一个或多个命令的定时。

公开(公告)号：WO2014085266A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/071532

申请日：2013-11-22

Applicant: INTEL CORPORATION ,  MCCALL, James A. ,  BAINS, Kuljit S.

Inventor： MCCALL, James A. ,  BAINS, Kuljit S.

IPC: G11C5/14 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C5/147 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028

Abstract: Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an embodiment, an input/output (I/O) interface of a memory device includes receiver circuits each to process a respective signal received via a corresponding signal line of a bus. In response to one or more configuration commands, a first receiver circuit is configured to process a first signal based on a first reference voltage level and a second receiver circuit is configured to process a second signal based on a second reference voltage level. In another embodiment, a memory controller sends the one or more configuration commands to such a memory device based on an evaluation of voltage swing characteristics each corresponding to a different respective signal line of a bus.

Abstract translation: 用于存储器件的技术和机制，用于基于不同的相应参考电压电平同时接收和处理信号。 在一个实施例中，存储器件的输入/输出（I / O）接口包括接收器电路，每个接收器电路用于处理经由总线的相应信号线接收的相应信号。 响应于一个或多个配置命令，第一接收器电路被配置为基于第一参考电压电平处理第一信号，并且第二接收器电路被配置为基于第二参考电压电平来处理第二信号。 在另一个实施例中，存储器控制器基于对每个对应于总线的不同相应信号线的电压摆动特性的评估将一个或多个配置命令发送到这种存储器设备。

公开(公告)号：WO2013109284A1

公开(公告)日：2013-07-25

申请号：PCT/US2012/021988

申请日：2012-01-20

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S. ,  SAH, Suneeta

Inventor： BAINS, Kuljit S. ,  SAH, Suneeta

IPC: G11C11/409 ,  G06F12/00

CPC classification number: G11C7/1072 ,  G11C11/4076

Abstract: Embodiments of an apparatus, system and method for using Per DRAM Addressability (PDA) to program Multi-Purpose Registers (MPRs) of a dynamic random access memory (DRAM) device are described herein. Embodiments of the invention allow unique 32 bit patterns to be stored for each DRAM device on a rank, thereby enabling data bus training to be done in parallel. Furthermore, embodiments of the invention provide 32 bits of storage per DRAM device on a rank for the system BIOS for storing codes such as MR values, or for any other purpose (e.g., temporary scratch storage to be used by BIOS processes).

Abstract translation: 本文描述了使用每DRAM可寻址性（PDA）来编程动态随机存取存储器（DRAM）设备的多用途寄存器（MPR）的装置，系统和方法的实施例。 本发明的实施例允许为等级上的每个DRAM设备存储唯一的32位模式，从而使数据总线训练能够并行完成。 此外，本发明的实施例在用于存储诸如MR值的代码或用于任何其它目的（例如，由BIOS处理使用的临时暂存）的系统BIOS的等级上为每个DRAM设备提供32位存储。

公开(公告)号：WO2008005781A2

公开(公告)日：2008-01-10

申请号：PCT/US2007/072295

申请日：2007-06-27

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S.

Inventor： BAINS, Kuljit S.

CPC classification number: G06F11/1008

Abstract: Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.

Abstract translation: 本发明的实施例通常旨在改善存储器装置的可靠性，可用性和可服务性。 在一些实施例中，存储器设备包括具有存储数据比特的第一部分和存储对应于数据比特的纠错码（ECC）比特的第二部分的存储器核心。 存储器装置还可以在与存储器核心相同的芯片上包括纠错逻辑。 在一些实施例中，错误校正逻辑使存储器设备能够计算ECC比特并将所存储的ECC比特与所计算的ECC比特进行比较。

公开(公告)号：WO2013002929A1

公开(公告)日：2013-01-03

申请号：PCT/US2012/039726

申请日：2012-05-25

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S. ,  VERGIS, George

Inventor： BAINS, Kuljit S. ,  VERGIS, George

IPC: G11C5/14 ,  G11C7/10

CPC classification number: G11C7/1045 ,  G11C5/04 ,  G11C7/1063

Abstract: Embodiments of the present disclosure describe memory module bus termination voltage (VTT) regulation and management techniques and configurations. A method includes receiving, by a register, a signal that is driven over a bus to a memory device comprising a plurality of memory cells and setting, within the register, a termination voltage (VTT) for the bus based on the signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了存储器模块总线终端电压（VTT）调节和管理技术和配置。 一种方法包括通过寄存器将通过总线驱动的信号接收到包括多个存储器单元的存储器件，并且根据该信号在寄存器内设置总线的终端电压（VTT）。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2012040730A1

公开(公告)日：2012-03-29

申请号：PCT/US2011/053315

申请日：2011-09-26

Applicant: INTEL CORPORATION ,  BAINS, Kuljit S.

Inventor： BAINS, Kuljit S.

IPC: G11C11/401 ,  G11C11/4063 ,  G06F12/00

CPC classification number: G11C11/40618 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/40622

Abstract: Embodiments of the invention describe systems, methods, and apparatuses to reduce the instantaneous power necessary to execute a DRAM device initiated self-refresh. Embodiments of the invention describe a DRAM device enabled to stagger self-refreshes between a plurality of banks. Staggering self-refreshes between banks reduces the current required for a DRAM self-refresh, thus reducing the amount of current required by the DRAM device.

Abstract translation: 本发明的实施例描述了用于减少执行DRAM设备启动的自刷新所需的瞬时功率的系统，方法和设备。 本发明的实施例描述了能够错开多个存储体之间的自刷新的DRAM器件。 银行之间交错的自刷新可以减少DRAM自刷新所需的电流，从而减少DRAM设备所需的电流。