公开(公告)号：WO2021252188A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/034194

申请日：2021-05-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FAY, Owen R. ,  RICHARDS, Randon K. ,  LIMAYE, Aparna U. ,  LIM, Dong Soon ,  YOO, Chan H. ,  STREET, Bret K. ,  NAKANO, Eiichi ,  LUO, Shijian

IPC: H01L25/10 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/552 ,  H01L23/66 ,  H01L23/34 ,  H01L25/18 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/1047 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/10 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50

Abstract: Disclosed are microelectronic device assemblies comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device having bond pads operably coupled to conductive traces in contact with the microelectronic devices and extending over a dielectric material to conductive via locations beyond at least one side of the stack for routing power and ground/bias extending through the dielectric materials to contact exposed conductors of the substrate. Data signals are routed between and through microelectronic devices of the stack by structure for data signal communication. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：WO2022147000A1

公开(公告)日：2022-07-07

申请号：PCT/US2021/065333

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KIM, Kang-Yong ,  LEE, Hyun Yoo ,  HOLLIS, Timothy M. ,  LIM, Dong Soon

IPC: H04L25/49 ,  H04L25/03

Abstract: Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit (460) can be coupled between an output and an input of a middle slicer (422). In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye (712) of the PAM4 signal. The other two eyes (710, 714) thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.

公开(公告)号：WO2022146997A1

公开(公告)日：2022-07-07

申请号：PCT/US2021/065330

申请日：2021-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KIM, Kang-Yong ,  LEE, Hyun Yoo ,  HOLLIS, Timothy M. ,  LIM, Dong Soon

IPC: G06F13/16 ,  G11C7/22

Abstract: Described apparatuses and methods enable communication between a host device (104) and a memory device (108) to establish relative delays between different data lines (304). If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect (106) having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command (122) indicative of a phase offset between two or more data lines (304, 306) of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets (312) between data lines (314, 316). The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：WO2021076274A1

公开(公告)日：2021-04-22

申请号：PCT/US2020/051727

申请日：2020-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FAY, Owen R. ,  RICHARDS, Randon K. ,  LIMAYE, Aparna U. ,  LIM, Dong Soon ,  YOO, Chan H. ,  STREET, Bret K. ,  NAKANO, Eiichi ,  LUO, Shijian

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/525 ,  H01L23/528 ,  H01L23/48 ,  H01L23/60

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.