公开(公告)号：WO2016089646A2

公开(公告)日：2016-06-09

申请号：PCT/US2015062092

申请日：2015-11-23

Applicant: QUALCOMM INC

Inventor： LI XIA ,  XU JEFFREY JUNHAO ,  WANG ZHONGZE ,  YANG BIN ,  CHEN XIAONAN ,  LU YU

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L21/28088 ,  G11C16/0408 ,  H01L21/02181 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a non-volatile memory device.

Abstract translation: 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，在非易失性存储器件中被实现为铁电偶极子层。

公开(公告)号：WO2016118376A3

公开(公告)日：2016-09-29

申请号：PCT/US2016013180

申请日：2016-01-13

Applicant: QUALCOMM INC

Inventor： YUAN JUN ,  LI XIA ,  YANG BIN

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391

Abstract: In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.

Abstract translation: 在特定实施例中，一种装置包括电子隧道结构。 电子隧道结构包括隧道层，沟道层，源极层和漏极层。 隧道层和沟道层位于源极层和漏极层之间。 晶体管器件还包括与电子隧道结构相邻的高k电介质层。

公开(公告)号：WO2013169776A2

公开(公告)日：2013-11-14

申请号：PCT/US2013039947

申请日：2013-05-07

Applicant: QUALCOMM INC

Inventor： YANG BIN ,  LI XIA ,  YUAN JUN

IPC: H01L21/84

CPC classification number: H01L21/823814 ,  H01L21/28026 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate.

Abstract translation: 公开了一种互补金属氧化物半导体（CMOS）器件及其形成方法。 在特定实施例中，CMOS器件包括硅衬底，硅衬底上的介电绝缘体材料以及介电绝缘体材料上的延伸层。 CMOS器件还包括与沟道接触并与延伸区域接触的栅极。 CMOS器件还包括与延伸区域接触的源极和与延伸区域接触的漏极。 延伸区域包括与源极和栅极接触的第一区域，并且包括与漏极和栅极接触的第二区域。